Refactor and fix LR/SC implementation (#217)

- Use physical addresses to avoid homonym ambiguity (closes #215)

- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)

- Don't yield reservation on exceptions (it's no longer required).

1 files changed, 1 insertions, 1 deletions

diff --git a/riscv/sim.cc b/riscv/sim.cc
index c9bbac0..b7080f0 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -109,7 +109,7 @@ void sim_t::step(size_t n)
     if (current_step == INTERLEAVE)
     {
       current_step = 0;
-      procs[current_proc]->yield_load_reservation();
+      procs[current_proc]->get_mmu()->yield_load_reservation();
       if (++current_proc == procs.size()) {
         current_proc = 0;
         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);