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author | Andrew Waterman <aswaterman@gmail.com> | 2018-07-10 09:56:32 -0700 |
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committer | GitHub <noreply@github.com> | 2018-07-10 09:56:32 -0700 |
commit | 95487c248a6eb660b9bd1aa49e28da5a1ab21059 (patch) | |
tree | 011bc774a4cb6eb647f0fbaca3cb4bc41cfe277b /riscv/sim.cc | |
parent | cc50a327a552f1aa84679c8d3020ec40edc2948f (diff) | |
download | riscv-isa-sim-95487c248a6eb660b9bd1aa49e28da5a1ab21059.zip riscv-isa-sim-95487c248a6eb660b9bd1aa49e28da5a1ab21059.tar.gz riscv-isa-sim-95487c248a6eb660b9bd1aa49e28da5a1ab21059.tar.bz2 |
Refactor and fix LR/SC implementation (#217)
- Use physical addresses to avoid homonym ambiguity (closes #215)
- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)
- Don't yield reservation on exceptions (it's no longer required).
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index c9bbac0..b7080f0 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -109,7 +109,7 @@ void sim_t::step(size_t n) if (current_step == INTERLEAVE) { current_step = 0; - procs[current_proc]->yield_load_reservation(); + procs[current_proc]->get_mmu()->yield_load_reservation(); if (++current_proc == procs.size()) { current_proc = 0; clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); |