diff options
author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 02:54:46 -0700 |
---|---|---|
committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-14 07:42:30 -0700 |
commit | 48fe0c484d50073bd5d12bdb7fef5b7ea257e006 (patch) | |
tree | 3ebf533ff93788a3d2cf71308df568df117c53b1 /riscv/sim.cc | |
parent | 9de0cdda3f089bf1a73d39eb1abb1dafe8cdbbab (diff) | |
download | riscv-isa-sim-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.zip riscv-isa-sim-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.tar.gz riscv-isa-sim-48fe0c484d50073bd5d12bdb7fef5b7ea257e006.tar.bz2 |
rvv: add varch option parser and initialize vector unit
the default vector parameters are defined in configuration time but can
be changed throught command-line option
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r-- | riscv/sim.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 0bfdc8b..2eb623a 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -24,8 +24,8 @@ static void handle_signal(int sig) signal(sig, &handle_signal); } -sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, - std::vector<std::pair<reg_t, mem_t*>> mems, +sim_t::sim_t(const char* isa, const char* varch, size_t nprocs, bool halted, + reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, std::vector<int> const hartids, const debug_module_config_t &dm_config) @@ -45,7 +45,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, if (hartids.size() == 0) { for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, i, halted); + procs[i] = new processor_t(isa, varch, this, i, halted); } } else { @@ -54,7 +54,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, exit(1); } for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, hartids[i], halted); + procs[i] = new processor_t(isa, varch, this, hartids[i], halted); } } |