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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:07:38 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:35 -0700 |
| commit | eadb0e1129c23e709b0565740f0fc1a3359de7b7 (patch) | |
| tree | 31e8a5fe6fa88892be4a330f8be2739d4d243119 /riscv/riscv.mk.in | |
| parent | 00873aa61acae4a17c1d269cddf1885e83b50102 (diff) | |
| download | riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.zip riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.tar.gz riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.tar.bz2 | |
Zvk: Implement Zvkned, vector AES single round
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption
& Decryption (Single Round)".
- vaeskf1.vi: AES forward key scheduling, AES-128.
- vaeskf2.vi: AES forward key scheduling, AES-256.
- vaesz.vs: AES encryption/decryption, 0-th round.
- vaesdm.{vs,vv}: AES decryption, middle rounds.
- vaesdf.{vs,vv}: AES decryption, final round.
- vaesem.{vs,vv}: AES encryption, middle rounds.
- vaesef.{vs,vv}: AES encryption, final round.
An extension specific header containing common logic is added.
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 4ce088f..2d75662 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1368,6 +1368,19 @@ riscv_insn_ext_zvkg= \ vghsh_vv \ vgmul_vv \ +riscv_insn_ext_zvkned = \ + vaesdf_vs \ + vaesdf_vv \ + vaesdm_vs \ + vaesdm_vv \ + vaesef_vs \ + vaesef_vv \ + vaesem_vs \ + vaesem_vv \ + vaeskf1_vi \ + vaeskf2_vi \ + vaesz_vs \ + # Covers both Zvknha and Zvkhnb. riscv_insn_ext_zvknh = \ vsha2cl_vv \ @@ -1378,6 +1391,7 @@ riscv_insn_ext_zvk = \ $(riscv_insn_ext_zvbb) \ $(riscv_insn_ext_zvbc) \ $(riscv_insn_ext_zvkg) \ + $(riscv_insn_ext_zvkned) \ $(riscv_insn_ext_zvknh) \ riscv_insn_list = \ |