Support RISC-V p-ext-proposal v0.9.2 (#637)

* rvp: add 8/16 bits add/sub simd instructions

* rvp: add 8/16 bits shift simd instructions

* rvp: add 8/16 bits compare simd instructions

* rvp: add 8/16 bits multiply simd instructions

* rvp: add 8/16 bits misc simd instructions

* rvp: add 8 bits unpacking simd instructions

* rvp: update suppported extention and add restriction

* rvp: update encoding.h and riscv.mk.in

* rvp: disasm: add simd instruction support

* rvp: update readme for p-ext simd instructions

* rvp: fix rvp support version

* rvp: update encoding.h generated from riscv-opcode p-ext branch

* rvp: rename some macro argument

* rvp: add pk[bb,bt,tt,tb][16,32] instructions

* rvp: add kadd32, [su]maqa[_su] instructions

* rvp: fix missing initial value of pd

* rvp: add msw 32x32 multiply & add instructions

* rvp: change to use extract64

* rvp: add msw 32x16 multiply & add instructions

* rvp: fix some style

* rvp: change reduction marcro definition

* rvp: add signed 16x32 add/subtract instructions

* rvp: use stdint to replace hardcode max/minimum

* rvp: refactor some p-ext macro code

* rvp: add partial simd miscellaneous instructions

* rvp: add signed 16 x 64 add/subtract Instructions

* rvp: add 64-bit add & sub instructions

* rvp: add 32-bit mul with 64-bit add/sub instructions

* rvp: add 16-bit mul with 64-bit add/sub instructions

* rvp: disasm: add 64 bit profile instruction support

* rvp: add Q15 saturation instructions

* rvp: fix kmar64/kmsr64 saturation behavior

* rvp: add 32-bit computation instructions

* rvp: add rdov/clrov and fix khm16 behavior of setting OV flag

* rvp: add non simd miscellaneous instructions

* rvp: add Q31 saturation instructions

* rvp: disasm: add non-simd instruction support

* rvp: add 32 bits add/sub simd instructions

* rvp: fix left shift saturation bug

* rvp: add 32 bits shift simd instructions

* rvp: add rv64 only Q15 simd instructions

* rvp: add rv64 only 32-bit multiply instructions

* rvp: add rv64 only 32-bit miscellaneous instructions

* rvp: add rv64 only 32-bit mul & add instructions

* rvp: add rv64 only 32-bit parallel mul & add instructions

* rvp: add rv64 only non-simd 32-bit shift instructions

* rvp: disasm: remove redundant tab

* rvp: disasm: add rv64 only instructions support

* rvp: change ov csr to ucode to match v0.5.2 spec

* rvp: update readme for p-ext 0.5.2

* rvp: update to p-ext v0.9.1

* rvp: update to p-ext v0.9.2

* rvp: update readme for p-ext 0.9.2

* rvp: fix macro for PKxx16 & PKxx32 commands.

* rvp: fix missing for in PKxxdd macro

* Sign-extension for p-ext insns

* * Fixed uclipNN insns while sh >> 64 is an UB.
* Added missing OV
* Added missing sext_xlen

* Remove unused macroses

* Sign extension for RD_PAIR macro

* rvp: remove lost tab

Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>

1 files changed, 345 insertions, 0 deletions

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 342ea56..055d6d1 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -907,6 +907,350 @@ riscv_insn_ext_h = \
 	hsv_w \
 	hsv_d \
 
+riscv_insn_ext_p_simd = \
+	add16 \
+	radd16 \
+	uradd16 \
+	kadd16 \
+	ukadd16 \
+	sub16 \
+	rsub16 \
+	ursub16 \
+	ksub16 \
+	uksub16 \
+	cras16 \
+	rcras16 \
+	urcras16 \
+	kcras16 \
+	ukcras16 \
+	crsa16 \
+	rcrsa16 \
+	urcrsa16 \
+	kcrsa16 \
+	ukcrsa16 \
+	stas16 \
+	rstas16 \
+	urstas16 \
+	kstas16 \
+	ukstas16 \
+	stsa16 \
+	rstsa16 \
+	urstsa16 \
+	kstsa16 \
+	ukstsa16 \
+	add8 \
+	radd8 \
+	uradd8 \
+	kadd8 \
+	ukadd8 \
+	sub8 \
+	rsub8 \
+	ursub8 \
+	ksub8 \
+	uksub8 \
+	sra16 \
+	srai16 \
+	sra16_u \
+	srai16_u \
+	srl16 \
+	srli16 \
+	srl16_u \
+	srli16_u \
+	sll16 \
+	slli16 \
+	ksll16 \
+	kslli16 \
+	kslra16 \
+	kslra16_u \
+	sra8 \
+	srai8 \
+	sra8_u \
+	srai8_u \
+	srl8 \
+	srli8 \
+	srl8_u \
+	srli8_u \
+	sll8 \
+	slli8 \
+	ksll8 \
+	kslli8 \
+	kslra8 \
+	kslra8_u \
+	cmpeq16 \
+	scmplt16 \
+	scmple16 \
+	ucmplt16 \
+	ucmple16 \
+	cmpeq8 \
+	scmplt8 \
+	scmple8 \
+	ucmplt8 \
+	ucmple8 \
+	smul16 \
+	smulx16 \
+	umul16 \
+	umulx16 \
+	khm16 \
+	khmx16 \
+	smul8 \
+	smulx8 \
+	umul8 \
+	umulx8 \
+	khm8 \
+	khmx8 \
+	smin16 \
+	umin16 \
+	smax16 \
+	umax16 \
+	sclip16 \
+	uclip16 \
+	kabs16 \
+	clrs16 \
+	clz16 \
+	clo16 \
+	swap16 \
+	smin8 \
+	umin8 \
+	smax8 \
+	umax8 \
+	sclip8 \
+	uclip8 \
+	kabs8 \
+	clrs8 \
+	clz8 \
+	clo8 \
+	swap8 \
+	sunpkd810 \
+	sunpkd820 \
+	sunpkd830 \
+	sunpkd831 \
+	sunpkd832 \
+	zunpkd810 \
+	zunpkd820 \
+	zunpkd830 \
+	zunpkd831 \
+	zunpkd832 \
+
+riscv_insn_ext_p_partial_simd = \
+	pkbb16 \
+	pkbt16 \
+	pktb16 \
+	pktt16 \
+	smmul \
+	smmul_u \
+	kmmac \
+	kmmac_u \
+	kmmsb \
+	kmmsb_u \
+	kwmmul \
+	kwmmul_u \
+	smmwb \
+	smmwb_u \
+	smmwt \
+	smmwt_u \
+	kmmawb \
+	kmmawb_u \
+	kmmawt \
+	kmmawt_u \
+	kmmwb2 \
+	kmmwb2_u \
+	kmmwt2 \
+	kmmwt2_u \
+	kmmawb2 \
+	kmmawb2_u \
+	kmmawt2 \
+	kmmawt2_u \
+	smbb16 \
+	smbt16 \
+	smtt16 \
+	kmda \
+	kmxda \
+	smds \
+	smdrs \
+	smxds \
+	kmabb \
+	kmabt \
+	kmatt \
+	kmada \
+	kmaxda \
+	kmads \
+	kmadrs \
+	kmaxds \
+	kmsda \
+	kmsxda \
+	smal \
+	sclip32 \
+	uclip32 \
+	clrs32 \
+	clz32 \
+	clo32 \
+	pbsad \
+	pbsada \
+	smaqa \
+	umaqa \
+	smaqa_su \
+
+riscv_insn_ext_p_64_bit_profile = \
+	add64 \
+	radd64 \
+	uradd64 \
+	kadd64 \
+	ukadd64 \
+	sub64 \
+	rsub64 \
+	ursub64 \
+	ksub64 \
+	uksub64 \
+	smar64 \
+	smsr64 \
+	umar64 \
+	umsr64 \
+	kmar64 \
+	kmsr64 \
+	ukmar64 \
+	ukmsr64 \
+	smalbb \
+	smalbt \
+	smaltt \
+	smalda \
+	smalxda \
+	smalds \
+	smaldrs \
+	smalxds \
+	smslda \
+	smslxda \
+
+riscv_insn_ext_p_non_simd = \
+	kaddh \
+	ksubh \
+	khmbb \
+	khmbt \
+	khmtt \
+	ukaddh \
+	uksubh \
+	kaddw \
+	ukaddw \
+	ksubw \
+	uksubw \
+	kdmbb \
+	kdmbt \
+	kdmtt \
+	kslraw \
+	kslraw_u \
+	ksllw \
+	kslliw \
+	kdmabb \
+	kdmabt \
+	kdmatt \
+	kabsw \
+	raddw \
+	uraddw \
+	rsubw \
+	ursubw \
+	maxw \
+	minw \
+	mulr64 \
+	mulsr64 \
+	msubr32 \
+	ave \
+	sra_u \
+	srai_u \
+	bitrev \
+	bitrevi \
+	wext \
+	wexti \
+	bpick \
+	insb \
+	maddr32 \
+
+riscv_insn_ext_p_rv64_only = \
+	add32 \
+	radd32 \
+	uradd32 \
+	kadd32 \
+	ukadd32 \
+	sub32 \
+	rsub32 \
+	ursub32 \
+	ksub32 \
+	uksub32 \
+	cras32 \
+	rcras32 \
+	urcras32 \
+	kcras32 \
+	ukcras32 \
+	crsa32 \
+	rcrsa32 \
+	urcrsa32 \
+	kcrsa32 \
+	ukcrsa32 \
+	stas32 \
+	rstas32 \
+	urstas32 \
+	kstas32 \
+	ukstas32 \
+	stsa32 \
+	rstsa32 \
+	urstsa32 \
+	kstsa32 \
+	ukstsa32 \
+	sra32 \
+	srai32 \
+	sra32_u \
+	srai32_u \
+	srl32 \
+	srli32 \
+	srl32_u \
+	srli32_u \
+	sll32 \
+	slli32 \
+	ksll32 \
+	kslli32 \
+	kslra32 \
+	kslra32_u \
+	smin32 \
+	umin32 \
+	smax32 \
+	umax32 \
+	kabs32 \
+	khmbb16 \
+	khmbt16 \
+	khmtt16 \
+	kdmbb16 \
+	kdmbt16 \
+	kdmtt16 \
+	kdmabb16 \
+	kdmabt16 \
+	kdmatt16 \
+	smbt32 \
+	smtt32 \
+	kmabb32 \
+	kmabt32 \
+	kmatt32 \
+	kmda32 \
+	kmxda32 \
+	kmaxda32 \
+	kmads32 \
+	kmadrs32 \
+	kmaxds32 \
+	kmsda32 \
+	kmsxda32 \
+	smds32 \
+	smdrs32 \
+	smxds32 \
+	sraiw_u \
+	pkbb32 \
+	pkbt32 \
+	pktb32 \
+	pktt32 \
+
+riscv_insn_ext_p = \
+	$(riscv_insn_ext_p_simd) \
+	$(riscv_insn_ext_p_partial_simd) \
+	$(riscv_insn_ext_p_64_bit_profile) \
+	$(riscv_insn_ext_p_non_simd) \
+	$(riscv_insn_ext_p_rv64_only) \
+
 riscv_insn_priv = \
 	csrrc \
 	csrrci \
@@ -936,6 +1280,7 @@ riscv_insn_list = \
     $(riscv_insn_ext_k) \
 	$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
 	$(riscv_insn_ext_h) \
+	$(riscv_insn_ext_p) \
 	$(riscv_insn_priv) \
 
 riscv_gen_srcs = \