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author | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-03-27 10:25:20 +0000 |
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committer | GitHub <noreply@github.com> | 2020-03-27 03:25:20 -0700 |
commit | bf296ca0643fa445b83d8bd45eefa3fca02d9921 (patch) | |
tree | 69222028c8870f885e7207959cafa8a83e4cbfce /riscv/processor.cc | |
parent | 66b44bfbedda562a32e4a2cd0716afbf731b69cd (diff) | |
download | riscv-isa-sim-bf296ca0643fa445b83d8bd45eefa3fca02d9921.zip riscv-isa-sim-bf296ca0643fa445b83d8bd45eefa3fca02d9921.tar.gz riscv-isa-sim-bf296ca0643fa445b83d8bd45eefa3fca02d9921.tar.bz2 |
Write execution logs to a named log file (#409)
This patch adds a --log argument to spike. If not given, the behaviour
is unchanged: messages logging execution of instructions and (if
commit logging is enabled) commits go to stderr.
If --log=P is given, Spike now writes these messages to a log file at
the path P. This is nice, because they are no longer tangled up with
other errors and warnings.
The code is mostly plumbing: passing a FILE* object through to the
functions that were using stderr. I've written a simple "log_file_t"
class, which opens a log file if necessary and yields it or stderr.
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r-- | riscv/processor.cc | 28 |
1 files changed, 12 insertions, 16 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 7ecdba0..a0ec42a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -21,10 +21,11 @@ #define STATE state processor_t::processor_t(const char* isa, const char* priv, const char* varch, - simif_t* sim, uint32_t id, bool halt_on_reset) + simif_t* sim, uint32_t id, bool halt_on_reset, + FILE* log_file) : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), xlen(0), histogram_enabled(false), log_commits_enabled(false), - halt_on_reset(halt_on_reset), last_pc(1), executions(1) + log_file(log_file), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { VU.p = this; parse_isa_string(isa); @@ -357,17 +358,12 @@ void processor_t::set_histogram(bool value) #endif } -void processor_t::set_log_commits(bool value) +#ifdef RISCV_ENABLE_COMMITLOG +void processor_t::enable_log_commits() { - log_commits_enabled = value; -#ifndef RISCV_ENABLE_COMMITLOG - if (value) { - fprintf(stderr, "Commit logging support has not been properly enabled;"); - fprintf(stderr, " please re-build the riscv-isa-sim project using \"configure --enable-commitlog\".\n"); - abort(); - } -#endif + log_commits_enabled = true; } +#endif void processor_t::reset() { @@ -477,11 +473,11 @@ void processor_t::enter_debug_mode(uint8_t cause) void processor_t::take_trap(trap_t& t, reg_t epc) { if (debug) { - fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", + fprintf(log_file, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", id, t.name(), epc); if (t.has_tval()) - fprintf(stderr, "core %3d: tval 0x%016" PRIx64 "\n", id, - t.get_tval()); + fprintf(log_file, "core %3d: tval 0x%016" PRIx64 "\n", + id, t.get_tval()); } if (state.debug_mode) { @@ -542,10 +538,10 @@ void processor_t::disasm(insn_t insn) uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); if (last_pc != state.pc || last_bits != bits) { if (executions != 1) { - fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions); + fprintf(log_file, "core %3d: Executed %" PRIx64 " times\n", id, executions); } - fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", + fprintf(log_file, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", id, state.pc, bits, disassembler->disassemble(insn).c_str()); last_pc = state.pc; last_bits = bits; |