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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-01 13:05:45 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-03-01 13:34:07 -0800 |
| commit | 9d3f3672039393675218268b447f5b039708265e (patch) | |
| tree | 8bded8bf073f54ca2511c9f110c75c80c04fd80f /riscv/plic.cc | |
| parent | 2ec72f2a84d77ac43044bf5593923468990d1b40 (diff) | |
| download | riscv-isa-sim-9d3f3672039393675218268b447f5b039708265e.zip riscv-isa-sim-9d3f3672039393675218268b447f5b039708265e.tar.gz riscv-isa-sim-9d3f3672039393675218268b447f5b039708265e.tar.bz2 | |
Fix PLIC on big-endian hosts
Diffstat (limited to 'riscv/plic.cc')
| -rw-r--r-- | riscv/plic.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/plic.cc b/riscv/plic.cc index 57355ef..515451a 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -329,7 +329,7 @@ bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes) } } - memcpy(bytes, (uint8_t *)&val, len); + read_little_endian_reg(val, addr, len, bytes); return ret; } @@ -337,7 +337,7 @@ bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes) bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes) { bool ret = false; - uint32_t val; + uint32_t val = 0; switch (len) { case 4: @@ -350,7 +350,7 @@ bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes) return false; } - memcpy((uint8_t *)&val, bytes, len); + write_little_endian_reg(&val, addr, len, bytes); if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) { ret = priority_write(addr, val); |