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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-01-12 01:19:15 +0100 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-01-31 09:34:41 -0800 |
commit | e69b20645654b498a4fdcd83ff2409037d1a5bf7 (patch) | |
tree | 74c8a3f5b7730117b31b284fce05bb1f3e334fef /riscv/isa_parser.h | |
parent | ba1e1b62860f58686d0e752b5f6a4079e1d1c22b (diff) | |
download | riscv-isa-sim-e69b20645654b498a4fdcd83ff2409037d1a5bf7.zip riscv-isa-sim-e69b20645654b498a4fdcd83ff2409037d1a5bf7.tar.gz riscv-isa-sim-e69b20645654b498a4fdcd83ff2409037d1a5bf7.tar.bz2 |
Zicond: implement Zicond (conditional integer operations)
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
Diffstat (limited to 'riscv/isa_parser.h')
-rw-r--r-- | riscv/isa_parser.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 01f4680..3ae9a16 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -53,6 +53,7 @@ typedef enum { EXT_ZICBOM, EXT_ZICBOZ, EXT_ZICNTR, + EXT_ZICOND, EXT_ZIHPM, EXT_XZBP, EXT_XZBS, |