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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:36:39 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 23:04:43 +0800 |
| commit | a8c3029a3cad0e61a18cdb61fe7454b67819cc4e (patch) | |
| tree | 13f0314c23568dcb224351a144dd8d98a71cd548 /riscv/isa_parser.h | |
| parent | 20b312615462b4f82665da54756261d632642e31 (diff) | |
| download | riscv-isa-sim-a8c3029a3cad0e61a18cdb61fe7454b67819cc4e.zip riscv-isa-sim-a8c3029a3cad0e61a18cdb61fe7454b67819cc4e.tar.gz riscv-isa-sim-a8c3029a3cad0e61a18cdb61fe7454b67819cc4e.tar.bz2 | |
Add isa string support for Zfbfmin/Zvfbfmin/Zvfbfwma
Diffstat (limited to 'riscv/isa_parser.h')
| -rw-r--r-- | riscv/isa_parser.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 9effd16..04859b6 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -49,6 +49,7 @@ typedef enum { EXT_SVINVAL, EXT_ZDINX, EXT_ZFA, + EXT_ZFBFMIN, EXT_ZFINX, EXT_ZHINX, EXT_ZHINXMIN, @@ -57,6 +58,8 @@ typedef enum { EXT_ZICNTR, EXT_ZICOND, EXT_ZIHPM, + EXT_ZVFBFMIN, + EXT_ZVFBFWMA, EXT_XZBP, EXT_XZBS, EXT_XZBE, |