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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
| commit | c8a8c07ec296ce36dc04f2448faf48fe1c502a2d (patch) | |
| tree | a497ddda532182cc10aa2f82a555e0d3ab4d220c /riscv/insns/mulhsu.h | |
| parent | 6554cdd3fb42bc3833a1888f87dfc67c9099500c (diff) | |
| download | riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.zip riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.gz riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.bz2 | |
Use WRITE_RD/WRITE_FRD macros to write registers
Diffstat (limited to 'riscv/insns/mulhsu.h')
| -rw-r--r-- | riscv/insns/mulhsu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h index c832657..d62256e 100644 --- a/riscv/insns/mulhsu.h +++ b/riscv/insns/mulhsu.h @@ -2,7 +2,7 @@ if(xpr64) { int64_t a = RS1; uint64_t b = RS2; - RD = (int128_t(a) * uint128_t(b)) >> 64; + WRITE_RD((int128_t(a) * uint128_t(b)) >> 64); } else - RD = sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32); + WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32)); |