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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-25 22:56:38 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-25 22:56:38 -0800 |
| commit | 76ee8711f8e04b9ada61e91e6ac6f1fd01a4ca1e (patch) | |
| tree | d3d838463115df47339cb2758d0c58424424d953 /riscv/insns/mulhsu.h | |
| parent | 5bae2bf37228d1a67d8f4c6175a6cda768d8b3e6 (diff) | |
| download | riscv-isa-sim-76ee8711f8e04b9ada61e91e6ac6f1fd01a4ca1e.zip riscv-isa-sim-76ee8711f8e04b9ada61e91e6ac6f1fd01a4ca1e.tar.gz riscv-isa-sim-76ee8711f8e04b9ada61e91e6ac6f1fd01a4ca1e.tar.bz2 | |
[sim,opcodes] add mulhsu instruction
Diffstat (limited to 'riscv/insns/mulhsu.h')
| -rw-r--r-- | riscv/insns/mulhsu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h new file mode 100644 index 0000000..506424d --- /dev/null +++ b/riscv/insns/mulhsu.h @@ -0,0 +1,8 @@ +if(xpr64) +{ + int64_t a = RS1; + uint64_t b = RS2; + RD = (int128_t(a) * uint128_t(b)) >> 64; +} +else + RD = sext32((sreg_t(RS1) * reg_t(RS2)) >> 32); |