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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-09-20 19:01:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-09-20 19:01:40 -0700 |
| commit | cbefaf68c7cbef82567036513c072de04585faca (patch) | |
| tree | 3e448540f1b4e0782aa37e319464c426f11e26f3 /riscv/insns/lwu.h | |
| parent | 1583b7a9e256107094946fccb0d22541c9902225 (diff) | |
| download | riscv-isa-sim-cbefaf68c7cbef82567036513c072de04585faca.zip riscv-isa-sim-cbefaf68c7cbef82567036513c072de04585faca.tar.gz riscv-isa-sim-cbefaf68c7cbef82567036513c072de04585faca.tar.bz2 | |
[xcc, sim] changed instruction format so imm12 subs for rs2
Diffstat (limited to 'riscv/insns/lwu.h')
| -rw-r--r-- | riscv/insns/lwu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index 311292d..3c597af 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1 +1 @@ -RA = mmu.load_uint32(RB+SIMM); +RDI = mmu.load_uint32(RS1+SIMM); |