diff options
| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
| commit | c8a8c07ec296ce36dc04f2448faf48fe1c502a2d (patch) | |
| tree | a497ddda532182cc10aa2f82a555e0d3ab4d220c /riscv/insns/lwu.h | |
| parent | 6554cdd3fb42bc3833a1888f87dfc67c9099500c (diff) | |
| download | riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.zip riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.gz riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.bz2 | |
Use WRITE_RD/WRITE_FRD macros to write registers
Diffstat (limited to 'riscv/insns/lwu.h')
| -rw-r--r-- | riscv/insns/lwu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index 6c4ad76..5535baf 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1,2 +1,2 @@ require_xpr64; -RD = MMU.load_uint32(RS1 + insn.i_imm()); +WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm())); |