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| author | Tim Newsome <tim@sifive.com> | 2016-05-04 18:51:26 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | dd233bc49946aa059b6ea9494b870d20076ce1b8 (patch) | |
| tree | c873d001c46e7935258091b1a938da53d54bbfd6 /riscv/insns/dret.h | |
| parent | 6ef848928a5e2d72d9b0aed66f669b7b9a80b49a (diff) | |
| download | riscv-isa-sim-dd233bc49946aa059b6ea9494b870d20076ce1b8.zip riscv-isa-sim-dd233bc49946aa059b6ea9494b870d20076ce1b8.tar.gz riscv-isa-sim-dd233bc49946aa059b6ea9494b870d20076ce1b8.tar.bz2 | |
Single step appears to work.
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 6cfd1e2..35c19cb 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -4,3 +4,6 @@ p->set_privilege(STATE.dcsr.prv); /* We're not in Debug Mode anymore. */ STATE.dcsr.cause = 0; + +if (STATE.dcsr.step) + STATE.single_step = STATE.STEP_STEPPING; |