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| author | Tim Newsome <tim@sifive.com> | 2016-07-28 14:51:31 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-07-28 14:51:31 -0700 |
| commit | 4fcc71ee8a23c3b4d96218a93a1842dab398be26 (patch) | |
| tree | f8360dd349fd2bb897eafab100a8fa38ee540e02 /riscv/insns/dret.h | |
| parent | 5daafcde73f448a702356e049911b5677a1811c2 (diff) | |
| download | riscv-isa-sim-4fcc71ee8a23c3b4d96218a93a1842dab398be26.zip riscv-isa-sim-4fcc71ee8a23c3b4d96218a93a1842dab398be26.tar.gz riscv-isa-sim-4fcc71ee8a23c3b4d96218a93a1842dab398be26.tar.bz2 | |
Add support for virtual priv register. (#59)
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 35c19cb..bef9ef2 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,6 +1,9 @@ require_privilege(PRV_M); set_pc_and_serialize(STATE.dpc); -p->set_privilege(STATE.dcsr.prv); +/* The debug spec says we can't crash when prv is set to an invalid value. */ +if (p->validate_priv(STATE.dcsr.prv)) { + p->set_privilege(STATE.dcsr.prv); +} /* We're not in Debug Mode anymore. */ STATE.dcsr.cause = 0; |