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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-06 01:54:38 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-06-14 07:36:45 -0700 |
commit | 004649e9e5d71d0a3ebb1e4d70711999aca91cbf (patch) | |
tree | d4992148a971eaa5fa295599fcf726c8eb69722c /configure.ac | |
parent | 3d7c84220971c6b1aee6e28779c8ebc71276d26a (diff) | |
download | riscv-isa-sim-004649e9e5d71d0a3ebb1e4d70711999aca91cbf.zip riscv-isa-sim-004649e9e5d71d0a3ebb1e4d70711999aca91cbf.tar.gz riscv-isa-sim-004649e9e5d71d0a3ebb1e4d70711999aca91cbf.tar.bz2 |
rvv: add configuration and command-line option
1. configure option "--with-varch"
the option defines the default u-arch implementatiton-decided parameter
VLEN: vector register length in bit
SLEN: striping distance in bit
ELEN: max element size in bit
ex: --with-vector=v128:e32:s128
2. add __int128_t type checking
3. add --varch command option and help message
ex: --varch=v512:e64:s512
Signed-off-by: Dave Wen <dave.wen@sifive.com>
Diffstat (limited to 'configure.ac')
-rw-r--r-- | configure.ac | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/configure.ac b/configure.ac index 6b28bf3..cc72d64 100644 --- a/configure.ac +++ b/configure.ac @@ -73,6 +73,13 @@ MCPPBS_PROG_INSTALL AC_HEADER_STDC #------------------------------------------------------------------------- +# Checks for type +#------------------------------------------------------------------------- + +AC_CHECK_TYPE([__int128_t], [], + [echo "error: spike requires 128 integer suuport"; exit 1], []) + +#------------------------------------------------------------------------- # Default compiler flags #------------------------------------------------------------------------- |