adding spike as a target to the arch-test-framework (#630)

* files and collateral for adding spike as a target to the arch-test-framework

* minor typo fix

Co-authored-by: Neel Gala <neelgala@incoresemi.com>

14 files changed, 567 insertions, 0 deletions

diff --git a/arch_test_target/spike/Makefile.include b/arch_test_target/spike/Makefile.include
new file mode 100644
index 0000000..13eacdc
--- /dev/null
+++ b/arch_test_target/spike/Makefile.include
@@ -0,0 +1,25 @@
+# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
+export TARGETDIR ?= /scratch/git-repo/github/neel/riscv-isa-sim/arch_test_target
+
+# set XLEN to max supported XLEN. Allowed values are 32 and 64
+export XLEN 							?= 64
+
+# name of the target. Note a folder of the same name must exist in the TARGETDIR directory
+export RISCV_TARGET       ?= spike
+
+# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify. 
+# Leave this blank if you want to iterate through all the supported extensions available in the target
+export RISCV_DEVICE       ?= 
+
+# set this to a string which needs to be passed to your target Makefile.include files
+export RISCV_TARGET_FLAGS ?= 
+
+# set this if you want to enable assertions on the test-suites. Currently no tests support
+# assertions.
+export RISCV_ASSERT       ?= 0
+
+# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure
+# that no common files across jobs are created/overwritten leading to unknown behavior
+JOBS= -j1
+
+
diff --git a/arch_test_target/spike/README.md b/arch_test_target/spike/README.md
new file mode 100644
index 0000000..ee12c43
--- /dev/null
+++ b/arch_test_target/spike/README.md
@@ -0,0 +1,56 @@
+# Using the Spike Simulator as an Architectural test model
+
+This is a reference for running Spike as a target for the RISC-V Architectural Test framework.
+
+## Getting Spike
+
+The Spike repository should be cloned from [here](https://github.com/riscv/riscv-isa-sim/), preferably at the same directory level as the riscv-compliance repository.
+
+## Building Spike
+
+The [README.md](../README.md) at the top level of the riscv-isa-sim directory gives details on building an executable spike model.
+
+## Adding Spike as a target to the Architectural Test framework
+
+Also at the top level is an ``arch_test_target directory``. This directory contains all the collaterals
+required to add Spike as a target to the architectural test framework.
+
+The user will have to modify the ``TARGETDIR`` variable in ``arch_test_target/spike/Makfile.include`` to point to the
+absolute address of the ``riscv-isa-sim/arch_test_target``. 
+
+The user can also modify the ``XLEN`` variable based on whether 32-bit or 64-bit tests need to be run.
+If you would like to run tests of a single extension then set the `RISCV_DEVICE` to that extension
+name (eg. M, C, Zifencei, etc). Leaving the ``RISCV_DEVICE`` empty would indicate running all tests
+for all extensions available in the ``device/rv{XLEN}i_m`` directory No other variables should be modified.
+
+Now clone the architectural test framework repo and copy the updated Makefile.include to it:
+
+```
+  $ git clone https://github.com/riscv/riscv-compliance.git
+  $ cd riscv-compliance
+  $ cp <custom-path>/riscv-isa-sim/arch_test_target/Makefile.include .
+```
+
+You can execute the tests from the root directory of the riscv-compliance repo:
+
+```
+make compile simulate verify
+```
+
+## Updating the target for new tests
+
+As tests for new extensions are added to the architectural test repo, the spike target (i.e.
+arch_test_target directory) will also need to be updated accordingly. Please refer to the [Porting a new target](https://github.com/riscv/riscv-compliance/blob/master/doc/README.adoc#5-porting-a-new-target)
+section for more details on what those changes/updates should be.
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/arch_test_target/spike/device/rv32i_m/C/Makefile.include b/arch_test_target/spike/device/rv32i_m/C/Makefile.include
new file mode 100644
index 0000000..7853baf
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/C/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv32i_m/I/Makefile.include b/arch_test_target/spike/device/rv32i_m/I/Makefile.include
new file mode 100644
index 0000000..6c3693c
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/I/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/device/rv32i_m/M/Makefile.include b/arch_test_target/spike/device/rv32i_m/M/Makefile.include
new file mode 100644
index 0000000..2f1e83c
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/M/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32im \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include b/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include
new file mode 100644
index 0000000..6c3693c
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include b/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include
new file mode 100644
index 0000000..2d55242
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/device/rv64i_m/C/Makefile.include b/arch_test_target/spike/device/rv64i_m/C/Makefile.include
new file mode 100644
index 0000000..4d95759
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/C/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ic \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv64i_m/I/Makefile.include b/arch_test_target/spike/device/rv64i_m/I/Makefile.include
new file mode 100644
index 0000000..20a1fdc
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/I/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64i \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/device/rv64i_m/M/Makefile.include b/arch_test_target/spike/device/rv64i_m/M/Makefile.include
new file mode 100644
index 0000000..0ae9f0a
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/M/Makefile.include
@@ -0,0 +1,41 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64im \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
+
diff --git a/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include b/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include
new file mode 100644
index 0000000..61916a2
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include
@@ -0,0 +1,41 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64i \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include b/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include
new file mode 100644
index 0000000..80e4a69
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM   ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ic \
+        +signature=$(*).signature.output +signature-granularity=4\
+        $< 
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/arch_test_target/spike/link.ld b/arch_test_target/spike/link.ld
new file mode 100644
index 0000000..8ad95e0
--- /dev/null
+++ b/arch_test_target/spike/link.ld
@@ -0,0 +1,18 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(rvtest_entry_point)
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text.init : { *(.text.init) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string)}
+  .bss : { *(.bss) }
+  _end = .;
+}
+
diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h
new file mode 100644
index 0000000..6aeb1c2
--- /dev/null
+++ b/arch_test_target/spike/model_test.h
@@ -0,0 +1,66 @@
+#ifndef _COMPLIANCE_MODEL_H

+#define _COMPLIANCE_MODEL_H

+

+#if XLEN == 64

+  #define ALIGNMENT 3

+#else

+  #define ALIGNMENT 2

+#endif

+

+#define RVMODEL_DATA_SECTION \

+        .pushsection .tohost,"aw",@progbits;                            \

+        .align 8; .global tohost; tohost: .dword 0;                     \

+        .align 8; .global fromhost; fromhost: .dword 0;                 \

+        .popsection;                                                    \

+        .align 8; .global begin_regstate; begin_regstate:               \

+        .word 128;                                                      \

+        .align 8; .global end_regstate; end_regstate:                   \

+        .word 4;

+

+//RV_COMPLIANCE_HALT

+#define RVMODEL_HALT                                              \

+  addi x1, x1, 4; \

+  li x1, 1;                                                                   \

+  write_tohost:                                                               \

+    sw x1, tohost, t5;                                                        \

+  self_loop:  j self_loop;

+

+#define RVMODEL_BOOT

+

+//RV_COMPLIANCE_DATA_BEGIN

+#define RVMODEL_DATA_BEGIN                                              \

+  .align 4; .global begin_signature; begin_signature:

+

+//RV_COMPLIANCE_DATA_END

+#define RVMODEL_DATA_END                                                      \

+  .align 4; .global end_signature; end_signature:  \

+  RVMODEL_DATA_SECTION                                                        \

+

+//RVTEST_IO_INIT

+#define RVMODEL_IO_INIT

+//RVTEST_IO_WRITE_STR

+#define RVMODEL_IO_WRITE_STR(_R, _STR)

+//RVTEST_IO_CHECK

+#define RVMODEL_IO_CHECK()

+//RVTEST_IO_ASSERT_GPR_EQ

+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)

+//RVTEST_IO_ASSERT_SFPR_EQ

+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)

+//RVTEST_IO_ASSERT_DFPR_EQ

+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)

+

+#define RVMODEL_SET_MSW_INT       \

+ li t1, 1;                         \

+ li t2, 0x2000000;                 \

+ sw t1, 0(t2);

+

+#define RVMODEL_CLEAR_MSW_INT     \

+ li t2, 0x2000000;                 \

+ sw x0, 0(t2);

+

+#define RVMODEL_CLEAR_MTIMER_INT

+

+#define RVMODEL_CLEAR_MEXT_INT

+

+#endif // _COMPLIANCE_MODEL_H

+