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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-11 13:50:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-11 13:50:45 -0700 |
| commit | 0c2fe4ad849a970c4b456580dabb0e12f3fe9702 (patch) | |
| tree | f80b3f4ca32f89fe8a2cba385e881691cd3d1fa2 /ChangeLog.md | |
| parent | db067bbe5b8c23e0ab08fbd01a0f2779cd664a59 (diff) | |
| download | riscv-isa-sim-0c2fe4ad849a970c4b456580dabb0e12f3fe9702.zip riscv-isa-sim-0c2fe4ad849a970c4b456580dabb0e12f3fe9702.tar.gz riscv-isa-sim-0c2fe4ad849a970c4b456580dabb0e12f3fe9702.tar.bz2 | |
Support S-mode vectored interrupts
Diffstat (limited to 'ChangeLog.md')
| -rw-r--r-- | ChangeLog.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/ChangeLog.md b/ChangeLog.md index e411491..b9fcd7e 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,5 +1,6 @@ Version 1.0.1-dev ----------------- +- Support S-mode vectored interrupts (i.e. stvec[0] is now writable). - Added `hasel` debug feature. - Added `--dm-no-abstract-csr` command-line option. - Renamed `--progsize` to `--dm-progsize`. |