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author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-08-27 13:57:03 -0700 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-08-27 13:57:03 -0700 |
commit | eb07f100a37c12d2c0eb5501394c6c09342985c8 (patch) | |
tree | 70ea03c93f2fb0e2100ac1b52ff9e01e03dfe0d8 | |
parent | 20cd44ade6f92142e87d67866d5e436cdf914e72 (diff) | |
download | riscv-isa-sim-eb07f100a37c12d2c0eb5501394c6c09342985c8.zip riscv-isa-sim-eb07f100a37c12d2c0eb5501394c6c09342985c8.tar.gz riscv-isa-sim-eb07f100a37c12d2c0eb5501394c6c09342985c8.tar.bz2 |
Use cmdline --priv flag when parsing proc configurations from DTB
-rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index a44aea9..115fc0c 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -195,7 +195,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, exit(1); } - procs.push_back(new processor_t(isa_str, DEFAULT_PRIV, + procs.push_back(new processor_t(isa_str, cfg->priv, cfg, this, hartid, halted, log_file.get(), sout_)); harts[hartid] = procs[cpu_idx]; |