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| author | Tim Newsome <tim@casualhacker.net> | 2024-09-05 13:41:25 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@casualhacker.net> | 2024-09-05 13:41:25 -0700 |
| commit | 9c5a20fbdb0e112f57a462b6a520ea5835ca00bb (patch) | |
| tree | 22970f6e8dc7a4b38ec24a1895a38e50b2f32aa7 | |
| parent | cb78f095ded11a980ea3b2609676b87c9339cb41 (diff) | |
| download | riscv-isa-sim-9c5a20fbdb0e112f57a462b6a520ea5835ca00bb.zip riscv-isa-sim-9c5a20fbdb0e112f57a462b6a520ea5835ca00bb.tar.gz riscv-isa-sim-9c5a20fbdb0e112f57a462b6a520ea5835ca00bb.tar.bz2 | |
Work if tcontrol doesn't exist.
| -rw-r--r-- | riscv/insns/mret.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 | ||||
| -rw-r--r-- | riscv/triggers.cc | 9 |
3 files changed, 10 insertions, 3 deletions
diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index 4172b75..71e488d 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -20,5 +20,5 @@ if (prev_virt && prev_prv == PRV_U) STATE.vsstatus->write(STATE.vsstatus->read() & ~SSTATUS_SDT); STATE.mstatus->write(s); if (STATE.mstatush) STATE.mstatush->write(s >> 32); // log mstatush change -STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0); +if (STATE.tcontrol) STATE.tcontrol->write((STATE.tcontrol->read() & CSR_TCONTROL_MPTE) ? (CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE) : 0); p->set_privilege(prev_prv, prev_virt); diff --git a/riscv/processor.cc b/riscv/processor.cc index 0b318f5..60f6a89 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -535,7 +535,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) state.elp = elp_t::NO_LP_EXPECTED; state.mstatus->write(s); if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change - state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0); + if (state.tcontrol) state.tcontrol->write((state.tcontrol->read() & CSR_TCONTROL_MTE) ? CSR_TCONTROL_MPTE : 0); set_privilege(PRV_M, false); } } diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 452b656..4553f87 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -55,11 +55,18 @@ void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept sselect = (sselect_t)((proc->extension_enabled_const('S') && get_field(val, CSR_TEXTRA_SSELECT(xlen)) <= SSELECT_MAXVAL) ? get_field(val, CSR_TEXTRA_SSELECT(xlen)) : SSELECT_IGNORE); } +static reg_t tcontrol_value(const state_t * state) { + if (state->tcontrol) + return state->tcontrol->read(); + else + return 0; +} + bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const noexcept { auto state = proc->get_state(); auto prv = use_prev_prv ? state->prev_prv : state->prv; auto v = use_prev_prv ? state->prev_v : state->v; - auto m_enabled = get_action() != 0 || (state->tcontrol->read() & CSR_TCONTROL_MTE); + auto m_enabled = get_action() != 0 || (tcontrol_value(state) & CSR_TCONTROL_MTE); return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc); } |