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| author | YenHaoChen <howard25336284@gmail.com> | 2024-09-03 08:56:02 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-09-03 08:57:06 +0800 |
| commit | 7f38a503d032adafc10b3e9eea006d65e464e991 (patch) | |
| tree | cb54ee502a1b1c709ab236d2afb43598c3bef459 | |
| parent | ff6210921127925582802bf7e7ad6952c0e0758f (diff) | |
| download | riscv-isa-sim-7f38a503d032adafc10b3e9eea006d65e464e991.zip riscv-isa-sim-7f38a503d032adafc10b3e9eea006d65e464e991.tar.gz riscv-isa-sim-7f38a503d032adafc10b3e9eea006d65e464e991.tar.bz2 | |
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions
| -rw-r--r-- | disasm/disasm.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index b5e8428..1741969 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1694,6 +1694,8 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) #define DISASM_OPIV__X__INSN(name, sign) DEFINE_VECTOR_VX(name##_vx) + #define DISASM_OPIV_MULTIPLYADD__X__INSN(name, sign) DEFINE_VECTOR_MULTIPLYADD_VX(name##_vx) + #define DEFINE_VECTOR_VVM(name) \ add_vector_vvm_insn(this, #name, match_##name, mask_##name | mask_vm) @@ -1854,10 +1856,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DISASM_OPIV_VX__INSN(vwmulu, 0); DISASM_OPIV_VX__INSN(vwmulsu, 0); DISASM_OPIV_VX__INSN(vwmul, 1); - DISASM_OPIV_VX__INSN(vwmaccu, 0); - DISASM_OPIV_VX__INSN(vwmacc, 1); - DISASM_OPIV__X__INSN(vwmaccus, 1); - DISASM_OPIV_VX__INSN(vwmaccsu, 0); + DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccu, 0); + DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmacc, 1); + DISASM_OPIV_MULTIPLYADD__X__INSN(vwmaccus, 1); + DISASM_OPIV_MULTIPLYADD_VX__INSN(vwmaccsu, 0); #undef DISASM_OPIV_VXI_INSN #undef DISASM_OPIV_VX__INSN |