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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-23 14:59:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-08-23 14:59:34 -0700 |
| commit | 73bc67839acf9577b075b8d314f6514dcab2afd2 (patch) | |
| tree | 8ea9d637377c4ca94af75f8febd41b508e914e1a | |
| parent | 5efbfcbfa4611eb530c0854b4165613b73582f2d (diff) | |
| download | riscv-isa-sim-73bc67839acf9577b075b8d314f6514dcab2afd2.zip riscv-isa-sim-73bc67839acf9577b075b8d314f6514dcab2afd2.tar.gz riscv-isa-sim-73bc67839acf9577b075b8d314f6514dcab2afd2.tar.bz2 | |
Fix exception priority for RV32E JAL/JALR
| -rw-r--r-- | riscv/decode_macros.h | 1 | ||||
| -rw-r--r-- | riscv/insns/jal.h | 1 | ||||
| -rw-r--r-- | riscv/insns/jalr.h | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h index e247487..1aa74fb 100644 --- a/riscv/decode_macros.h +++ b/riscv/decode_macros.h @@ -22,6 +22,7 @@ #define RS2 READ_REG(insn.rs2()) #define RS3 READ_REG(insn.rs3()) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) +#define CHECK_RD() CHECK_REG(insn.rd()) /* 0 : int * 1 : floating diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h index cd59964..e7a75c7 100644 --- a/riscv/insns/jal.h +++ b/riscv/insns/jal.h @@ -1,3 +1,4 @@ +CHECK_RD(); reg_t tmp = npc; set_pc(JUMP_TARGET); WRITE_RD(tmp); diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h index 0606f67..de84e89 100644 --- a/riscv/insns/jalr.h +++ b/riscv/insns/jalr.h @@ -1,3 +1,4 @@ +CHECK_RD(); reg_t tmp = npc; set_pc((RS1 + insn.i_imm()) & ~reg_t(1)); WRITE_RD(tmp); |