diff options
| author | YenHaoChen <howard25336284@gmail.com> | 2024-08-26 14:18:51 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-08-26 14:18:53 +0800 |
| commit | 71bdc3bbd13a635637d730b2152aff912a929074 (patch) | |
| tree | 34e768c67df24b5babdf435016f3f89c2515d83f | |
| parent | 1b80449f017d78d8809a899cc7616d6959bc183e (diff) | |
| download | riscv-isa-sim-71bdc3bbd13a635637d730b2152aff912a929074.zip riscv-isa-sim-71bdc3bbd13a635637d730b2152aff912a929074.tar.gz riscv-isa-sim-71bdc3bbd13a635637d730b2152aff912a929074.tar.bz2 | |
pointer masking: Pointer masking does not apply when MXR=1 regardless of MPRV in v1.0.0-rc2
Reference: https://github.com/riscv/riscv-j-extension/issues/70
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 5d34541..e827f4a 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -614,7 +614,7 @@ void mmu_t::register_memtracer(memtracer_t* t) } reg_t mmu_t::get_pmlen(bool effective_virt, reg_t effective_priv, xlate_flags_t flags) const { - if (!proc || proc->get_xlen() != 64 || (in_mprv() && (proc->state.sstatus->read() & MSTATUS_MXR)) || flags.hlvx) + if (!proc || proc->get_xlen() != 64 || (proc->state.sstatus->read() & MSTATUS_MXR) || flags.hlvx) return 0; reg_t pmm = 0; |