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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-30 15:32:37 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-30 15:32:37 -0500 |
| commit | 3c5b1bb09ef6daf4146e311d1303cb8dd67c5ff3 (patch) | |
| tree | cc7c3679d9fe5400ddcd1975f1c1a36672a23e5e | |
| parent | 3f556d66e286bb41fe3013b2ece39c08c696b3fc (diff) | |
| parent | a1506ec006bad9c727652a5f7fbfe91c52572565 (diff) | |
| download | riscv-isa-sim-3c5b1bb09ef6daf4146e311d1303cb8dd67c5ff3.zip riscv-isa-sim-3c5b1bb09ef6daf4146e311d1303cb8dd67c5ff3.tar.gz riscv-isa-sim-3c5b1bb09ef6daf4146e311d1303cb8dd67c5ff3.tar.bz2 | |
Merge pull request #1779 from rtwfroody/trigger_timing
For mcontrol6, default to BEFORE timing.
| -rw-r--r-- | riscv/triggers.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 5e877d1..452b656 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -265,7 +265,14 @@ bool mcontrol_common_t::legalize_timing(reg_t val, reg_t timing_mask, reg_t sele return TIMING_AFTER; if (get_field(val, execute_mask)) return TIMING_BEFORE; - return get_field(val, timing_mask); + if (timing_mask) { + // Use the requested timing. + return get_field(val, timing_mask); + } else { + // For mcontrol6 you can't request a timing. Default to before since that's + // most useful to the user. + return TIMING_BEFORE; + } } reg_t mcontrol6_t::tdata1_read(const processor_t * const proc) const noexcept { |