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author | Andrew Waterman <andrew@sifive.com> | 2023-03-20 20:22:04 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2023-03-20 20:22:04 -0700 |
commit | e3689fc92a980f804315201743a44a2e8a3bbd29 (patch) | |
tree | 6304d37738f4a0659deb4f87a9839fd9ff26a7b0 | |
parent | f29dcd0d34bfc8c7d8982c9d03dc2e40bbc2f212 (diff) | |
parent | a5fdc4efbf9f79a890fe5d1c144880548b011d90 (diff) | |
download | riscv-isa-sim-e3689fc92a980f804315201743a44a2e8a3bbd29.zip riscv-isa-sim-e3689fc92a980f804315201743a44a2e8a3bbd29.tar.gz riscv-isa-sim-e3689fc92a980f804315201743a44a2e8a3bbd29.tar.bz2 |
Merge pull request #1286 from riscv-software-src/smrnmi
Implement Smrnmi extension
-rw-r--r-- | riscv/csrs.cc | 20 | ||||
-rw-r--r-- | riscv/csrs.h | 7 | ||||
-rw-r--r-- | riscv/encoding.h | 56 | ||||
-rw-r--r-- | riscv/insns/mnret.h | 15 | ||||
-rw-r--r-- | riscv/isa_parser.cc | 2 | ||||
-rw-r--r-- | riscv/isa_parser.h | 1 | ||||
-rw-r--r-- | riscv/mmu.cc | 4 | ||||
-rw-r--r-- | riscv/mmu.h | 8 | ||||
-rw-r--r-- | riscv/processor.cc | 19 | ||||
-rw-r--r-- | riscv/processor.h | 2 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 4 |
11 files changed, 93 insertions, 45 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 5cadfbe..2e01983 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -516,6 +516,24 @@ reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { | 0; // initial value for mstatus } +// implement class mnstatus_csr_t +mnstatus_csr_t::mnstatus_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool mnstatus_csr_t::unlogged_write(const reg_t val) noexcept { + // NMIE can be set but not cleared + const reg_t mask = (~read() & MNSTATUS_NMIE) + | (proc->extension_enabled('H') ? MNSTATUS_MNPV : 0) + | MNSTATUS_MNPP; + + const reg_t requested_mnpp = proc->legalize_privilege(get_field(val, MNSTATUS_MNPP)); + const reg_t adjusted_val = set_field(val, MNSTATUS_MNPP, requested_mnpp); + const reg_t new_mnstatus = (read() & ~mask) | (adjusted_val & mask); + + return basic_csr_t::unlogged_write(new_mnstatus); +} + // implement class rv32_low_csr_t rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): csr_t(proc, addr), @@ -654,7 +672,9 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { | (1 << CAUSE_VIRTUAL_INSTRUCTION) | (1 << CAUSE_STORE_GUEST_PAGE_FAULT) ; + state->medeleg->write(state->medeleg->read() & ~hypervisor_exceptions); + if (state->mnstatus) state->mnstatus->write(state->mnstatus->read() & ~MNSTATUS_MNPV); const reg_t new_mstatus = state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV); state->mstatus->write(new_mstatus); if (state->mstatush) state->mstatush->write(new_mstatus >> 32); // log mstatush change diff --git a/riscv/csrs.h b/riscv/csrs.h index 5dab1fc..65be799 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -256,6 +256,13 @@ class mstatus_csr_t final: public base_status_csr_t { typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p; +class mnstatus_csr_t final: public basic_csr_t { + public: + mnstatus_csr_t(processor_t* const proc, const reg_t addr); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + // For RV32 CSRs that are split into two, e.g. mstatus/mstatush // CSRW should only modify the lower half class rv32_low_csr_t: public csr_t { diff --git a/riscv/encoding.h b/riscv/encoding.h index ef70f5a..5ef5393 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (87a8824) + * https://github.com/riscv/riscv-opcodes (02b4866) */ #ifndef RISCV_CSR_ENCODING_H @@ -72,6 +72,10 @@ #define USTATUS_UIE 0x00000001 #define USTATUS_UPIE 0x00000010 +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPP 0x00001800 +#define MNSTATUS_MNPV 0x00000080 + #define DCSR_XDEBUGVER (3U<<30) #define DCSR_NDRESET (1<<29) #define DCSR_FULLRESET (1<<28) @@ -481,10 +485,6 @@ #define MASK_BINV 0xfe00707f #define MATCH_BINVI 0x68001013 #define MASK_BINVI 0xfc00707f -#define MATCH_BITREV 0xe6000077 -#define MASK_BITREV 0xfe00707f -#define MATCH_BITREVI 0xe8000077 -#define MASK_BITREVI 0xfc00707f #define MATCH_BLT 0x4063 #define MASK_BLT 0x707f #define MATCH_BLTU 0x6063 @@ -497,8 +497,6 @@ #define MASK_BMATXOR 0xfe00707f #define MATCH_BNE 0x1063 #define MASK_BNE 0x707f -#define MATCH_BPICK 0x3077 -#define MASK_BPICK 0x600707f #define MATCH_BSET 0x28001033 #define MASK_BSET 0xfe00707f #define MATCH_BSETI 0x28001013 @@ -625,12 +623,6 @@ #define MASK_CLMULH 0xfe00707f #define MATCH_CLMULR 0xa002033 #define MASK_CLMULR 0xfe00707f -#define MATCH_CLO16 0xaeb00077 -#define MASK_CLO16 0xfff0707f -#define MATCH_CLO32 0xafb00077 -#define MASK_CLO32 0xfff0707f -#define MATCH_CLO8 0xae300077 -#define MASK_CLO8 0xfff0707f #define MATCH_CLRS16 0xae800077 #define MASK_CLRS16 0xfff0707f #define MATCH_CLRS32 0xaf800077 @@ -1299,14 +1291,12 @@ #define MASK_MAX 0xfe00707f #define MATCH_MAXU 0xa007033 #define MASK_MAXU 0xfe00707f -#define MATCH_MAXW 0xf2000077 -#define MASK_MAXW 0xfe00707f #define MATCH_MIN 0xa004033 #define MASK_MIN 0xfe00707f #define MATCH_MINU 0xa005033 #define MASK_MINU 0xfe00707f -#define MATCH_MINW 0xf0000077 -#define MASK_MINW 0xfe00707f +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff #define MATCH_MRET 0x30200073 #define MASK_MRET 0xffffffff #define MATCH_MSUBR32 0xc6001077 @@ -1349,8 +1339,6 @@ #define MASK_PBSADA 0xfe00707f #define MATCH_PKBB16 0xe001077 #define MASK_PKBB16 0xfe00707f -#define MATCH_PKBB32 0xe002077 -#define MASK_PKBB32 0xfe00707f #define MATCH_PKBT16 0x1e001077 #define MASK_PKBT16 0xfe00707f #define MATCH_PKBT32 0x1e002077 @@ -1361,8 +1349,6 @@ #define MASK_PKTB32 0xfe00707f #define MATCH_PKTT16 0x2e001077 #define MASK_PKTT16 0xfe00707f -#define MATCH_PKTT32 0x2e002077 -#define MASK_PKTT32 0xfe00707f #define MATCH_PREFETCH_I 0x6013 #define MASK_PREFETCH_I 0x1f07fff #define MATCH_PREFETCH_R 0x106013 @@ -1755,8 +1741,6 @@ #define MASK_SUNPKD832 0xfff0707f #define MATCH_SW 0x2023 #define MASK_SW 0x707f -#define MATCH_SWAP8 0xad800077 -#define MASK_SWAP8 0xfff0707f #define MATCH_UCLIP16 0x85000077 #define MASK_UCLIP16 0xff00707f #define MATCH_UCLIP32 0xf4000077 @@ -2777,10 +2761,6 @@ #define MASK_VZEXT_VF4 0xfc0ff07f #define MATCH_VZEXT_VF8 0x48012057 #define MASK_VZEXT_VF8 0xfc0ff07f -#define MATCH_WEXT 0xce000077 -#define MASK_WEXT 0xfe00707f -#define MATCH_WEXTI 0xde000077 -#define MASK_WEXTI 0xfe00707f #define MATCH_WFI 0x10500073 #define MASK_WFI 0xffffffff #define MATCH_WRS_NTO 0xd00073 @@ -3205,6 +3185,10 @@ #define CSR_MHPMEVENT29H 0x73d #define CSR_MHPMEVENT30H 0x73e #define CSR_MHPMEVENT31H 0x73f +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 #define CSR_MSECCFGH 0x757 #define CSR_MCYCLEH 0xb80 #define CSR_MINSTRETH 0xb82 @@ -3415,15 +3399,12 @@ DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) -DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV) -DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK) DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) @@ -3487,9 +3468,6 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) -DECLARE_INSN(clo16, MATCH_CLO16, MASK_CLO16) -DECLARE_INSN(clo32, MATCH_CLO32, MASK_CLO32) -DECLARE_INSN(clo8, MATCH_CLO8, MASK_CLO8) DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) @@ -3824,10 +3802,9 @@ DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) DECLARE_INSN(max, MATCH_MAX, MASK_MAX) DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) -DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW) DECLARE_INSN(min, MATCH_MIN, MASK_MIN) DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) -DECLARE_INSN(minw, MATCH_MINW, MASK_MINW) +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) @@ -3849,13 +3826,11 @@ DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) -DECLARE_INSN(pkbb32, MATCH_PKBB32, MASK_PKBB32) DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) -DECLARE_INSN(pktt32, MATCH_PKTT32, MASK_PKTT32) DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) @@ -4052,7 +4027,6 @@ DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(swap8, MATCH_SWAP8, MASK_SWAP8) DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) @@ -4563,8 +4537,6 @@ DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) -DECLARE_INSN(wext, MATCH_WEXT, MASK_WEXT) -DECLARE_INSN(wexti, MATCH_WEXTI, MASK_WEXTI) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) @@ -4975,6 +4947,10 @@ DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) +DECLARE_CSR(mnscratch, CSR_MNSCRATCH) +DECLARE_CSR(mnepc, CSR_MNEPC) +DECLARE_CSR(mncause, CSR_MNCAUSE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS) DECLARE_CSR(mseccfgh, CSR_MSECCFGH) DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(minstreth, CSR_MINSTRETH) diff --git a/riscv/insns/mnret.h b/riscv/insns/mnret.h new file mode 100644 index 0000000..bc69510 --- /dev/null +++ b/riscv/insns/mnret.h @@ -0,0 +1,15 @@ +require_extension(EXT_SMRNMI); +require_privilege(PRV_M); +set_pc_and_serialize(p->get_state()->mnepc->read()); +reg_t s = STATE.mnstatus->read(); +reg_t prev_prv = get_field(s, MNSTATUS_MNPP); +reg_t prev_virt = get_field(s, MNSTATUS_MNPV); +if (prev_prv != PRV_M) { + reg_t mstatus = STATE.mstatus->read(); + mstatus = set_field(mstatus, MSTATUS_MPRV, 0); + STATE.mstatus->write(mstatus); +} +s = set_field(s, MNSTATUS_NMIE, 1); +STATE.mnstatus->write(s); +p->set_privilege(prev_prv); +p->set_virt(prev_virt); diff --git a/riscv/isa_parser.cc b/riscv/isa_parser.cc index 4fc53f7..caf91ea 100644 --- a/riscv/isa_parser.cc +++ b/riscv/isa_parser.cc @@ -211,6 +211,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SMEPMP] = true; } else if (ext_str == "smstateen") { extension_table[EXT_SMSTATEEN] = true; + } else if (ext_str == "smrnmi") { + extension_table[EXT_SMRNMI] = true; } else if (ext_str == "sscofpmf") { extension_table[EXT_SSCOFPMF] = true; } else if (ext_str == "svadu") { diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index a4c0ee5..090a9b5 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -41,6 +41,7 @@ typedef enum { EXT_ZVFHMIN, EXT_SMEPMP, EXT_SMSTATEEN, + EXT_SMRNMI, EXT_SSCOFPMF, EXT_SVADU, EXT_SVNAPOT, diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 8ce7a3a..be24f40 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -61,7 +61,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f bool hlvx = xlate_flags & RISCV_XLATE_VIRT_HLVX; reg_t mode = proc->state.prv; if (type != FETCH) { - if (!proc->state.debug_mode && get_field(proc->state.mstatus->read(), MSTATUS_MPRV)) { + if (in_mprv()) { mode = get_field(proc->state.mstatus->read(), MSTATUS_MPP); if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M) virt = true; @@ -307,7 +307,7 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; - if (proc && get_field(proc->state.mstatus->read(), MSTATUS_MPRV)) + if (in_mprv()) return entry; if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) diff --git a/riscv/mmu.h b/riscv/mmu.h index 56789e0..ef054cf 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -403,6 +403,14 @@ private: return (uint16_t*)(translate_insn_addr(addr).host_offset + addr); } + inline bool in_mprv() + { + return proc != nullptr + && !(proc->state.mnstatus && !get_field(proc->state.mnstatus->read(), MNSTATUS_NMIE)) + && !proc->state.debug_mode + && get_field(proc->state.mstatus->read(), MSTATUS_MPRV); + } + reg_t pmp_homogeneous(reg_t addr, reg_t len); bool pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode); diff --git a/riscv/processor.cc b/riscv/processor.cc index ad93a42..c05bdac 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -494,6 +494,13 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) } } + if (proc->extension_enabled_const(EXT_SMRNMI)) { + csrmap[CSR_MNSCRATCH] = std::make_shared<basic_csr_t>(proc, CSR_MNSCRATCH, 0); + csrmap[CSR_MNEPC] = mnepc = std::make_shared<epc_csr_t>(proc, CSR_MNEPC); + csrmap[CSR_MNCAUSE] = std::make_shared<const_csr_t>(proc, CSR_MNCAUSE, (reg_t)1 << (xlen - 1)); + csrmap[CSR_MNSTATUS] = mnstatus = std::make_shared<mnstatus_csr_t>(proc, CSR_MNSTATUS); + } + if (proc->extension_enabled_const(EXT_SSTC)) { stimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_STIMECMP, MIP_STIP); vstimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_VSTIMECMP, MIP_VSTIP); @@ -660,7 +667,8 @@ void processor_t::take_interrupt(reg_t pending_interrupts) } } - if (!state.debug_mode && enabled_interrupts) { + const bool nmie = !(state.mnstatus && !get_field(state.mnstatus->read(), MNSTATUS_NMIE)); + if (!state.debug_mode && nmie && enabled_interrupts) { // nonstandard interrupts have highest priority if (enabled_interrupts >> (IRQ_M_EXT + 1)) enabled_interrupts = enabled_interrupts >> (IRQ_M_EXT + 1) << (IRQ_M_EXT + 1); @@ -849,8 +857,13 @@ void processor_t::take_trap(trap_t& t, reg_t epc) } else { // Handle the trap in M-mode set_virt(false); - reg_t vector = (state.mtvec->read() & 1) && interrupt ? 4 * bit : 0; - state.pc = (state.mtvec->read() & ~(reg_t)1) + vector; + const reg_t vector = (state.mtvec->read() & 1) && interrupt ? 4 * bit : 0; + const reg_t trap_handler_address = (state.mtvec->read() & ~(reg_t)1) + vector; + // RNMI exception vector is implementation-defined. Since we don't model + // RNMI sources, the feature isn't very useful, so pick an invalid address. + const reg_t rnmi_trap_handler_address = 0; + const bool nmie = !(state.mnstatus && !get_field(state.mnstatus->read(), MNSTATUS_NMIE)); + state.pc = !nmie ? rnmi_trap_handler_address : trap_handler_address; state.mepc->write(epc); state.mcause->write(t.cause()); state.mtval->write(t.get_tval()); diff --git a/riscv/processor.h b/riscv/processor.h index 958c76a..60cfd04 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -99,6 +99,8 @@ struct state_t csr_t_p mideleg; csr_t_p mcounteren; csr_t_p mevent[N_HPMCOUNTERS]; + csr_t_p mnstatus; + csr_t_p mnepc; csr_t_p scounteren; csr_t_p sepc; csr_t_p stval; diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 8f7ac83..f64711a 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1265,6 +1265,9 @@ riscv_insn_priv = \ sret \ wfi \ +riscv_insn_smrnmi = \ + mnret \ + riscv_insn_svinval = \ sfence_w_inval \ sfence_inval_ir \ @@ -1329,6 +1332,7 @@ riscv_insn_list = \ $(riscv_insn_ext_p) \ $(riscv_insn_priv) \ $(riscv_insn_svinval) \ + $(riscv_insn_smrnmi) \ $(riscv_insn_ext_cmo) \ $(riscv_insn_ext_zicond) \ |