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| author | rbuchner <ryan.buchner@arilinc.com> | 2023-04-24 16:59:34 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
| commit | bd675766091549e4fc1607f6106b0dce7dc03d21 (patch) | |
| tree | edadb04ae2e58acfad3feddc7a6e97e03f305ae9 | |
| parent | 9312137ae2a218632ec293ecc12da7c72fa828b2 (diff) | |
| download | riscv-isa-sim-bd675766091549e4fc1607f6106b0dce7dc03d21.zip riscv-isa-sim-bd675766091549e4fc1607f6106b0dce7dc03d21.tar.gz riscv-isa-sim-bd675766091549e4fc1607f6106b0dce7dc03d21.tar.bz2 | |
Use access_info.effective_virt when failed mmio_load (i.e. device detects access fault)
Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index acbf652..db6c31e 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -214,7 +214,7 @@ void mmu_t::load_slow_path_intrapage(reg_t len, uint8_t* bytes, mem_access_info_ refill_tlb(addr, paddr, host_addr, LOAD); } else if (!mmio_load(paddr, len, bytes)) { - throw trap_load_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + throw trap_load_access_fault(access_info.effective_virt, addr, 0, 0); } if (access_info.flags.lr) { |