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| author | rbuchner <ryan.buchner@arilinc.com> | 2023-04-24 16:47:28 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:58 -0700 |
| commit | 9312137ae2a218632ec293ecc12da7c72fa828b2 (patch) | |
| tree | 7a4ab489306619722d222962ce05cbd656f1b119 | |
| parent | 87690a5ed4b55a3938efac098ce68fbf4d7fb037 (diff) | |
| download | riscv-isa-sim-9312137ae2a218632ec293ecc12da7c72fa828b2.zip riscv-isa-sim-9312137ae2a218632ec293ecc12da7c72fa828b2.tar.gz riscv-isa-sim-9312137ae2a218632ec293ecc12da7c72fa828b2.tar.bz2 | |
Use access_info.effective_virt when access_fault due to non-reservable lr
Fixes case 4 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 34cd170..acbf652 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -203,7 +203,7 @@ void mmu_t::load_slow_path_intrapage(reg_t len, uint8_t* bytes, mem_access_info_ reg_t paddr = translate(access_info, len); if (access_info.flags.lr && !sim->reservable(paddr)) { - throw trap_load_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + throw trap_load_access_fault(access_info.effective_virt, addr, 0, 0); } if (auto host_addr = sim->addr_to_mem(paddr)) { |