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| author | rbuchner <ryan.buchner@arilinc.com> | 2023-04-18 14:06:12 -0700 |
|---|---|---|
| committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
| commit | 4b9996bad9a3327b13056f21b7b2e03fdc41f65a (patch) | |
| tree | 7e6273451e63ee9401a16c2573cce71479ea1092 | |
| parent | f7900e4730e1c13fa42789bc01d8f0366756130e (diff) | |
| download | riscv-isa-sim-4b9996bad9a3327b13056f21b7b2e03fdc41f65a.zip riscv-isa-sim-4b9996bad9a3327b13056f21b7b2e03fdc41f65a.tar.gz riscv-isa-sim-4b9996bad9a3327b13056f21b7b2e03fdc41f65a.tar.bz2 | |
Pass mem_access_info_t into walk()
| -rw-r--r-- | riscv/mmu.cc | 10 | ||||
| -rw-r--r-- | riscv/mmu.h | 2 |
2 files changed, 8 insertions, 4 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 7264ea8..f40ce30 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -60,10 +60,9 @@ reg_t mmu_t::translate(mem_access_info_t access_info, reg_t len) return addr; bool virt = access_info.effective_virt; - bool hlvx = access_info.flags.hlvx; reg_t mode = (reg_t) access_info.effective_priv; - reg_t paddr = walk(addr, type, mode, virt, hlvx) | (addr & (PGSIZE-1)); + reg_t paddr = walk(access_info) | (addr & (PGSIZE-1)); if (!pmp_ok(paddr, len, type, mode)) throw_access_exception(virt, addr, type); return paddr; @@ -461,8 +460,13 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty } } -reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx) +reg_t mmu_t::walk(mem_access_info_t access_info) { + access_type type = access_info.type; + reg_t addr = access_info.vaddr; + bool virt = access_info.effective_virt; + bool hlvx = access_info.flags.hlvx; + reg_t mode = access_info.effective_priv; reg_t page_mask = (reg_t(1) << PGSHIFT) - 1; reg_t satp = proc->get_state()->satp->readvirt(virt); vm_info vm = decode_vm_info(proc->get_const_xlen(), false, mode, satp); diff --git a/riscv/mmu.h b/riscv/mmu.h index 41f6751..7d14ad5 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -374,7 +374,7 @@ private: reg_t s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_type, bool virt, bool hlvx); // perform a page table walk for a given VA; set referenced/dirty bits - reg_t walk(reg_t addr, access_type type, reg_t prv, bool virt, bool hlvx); + reg_t walk(mem_access_info_t access_info); // handle uncommon cases: TLB misses, page faults, MMIO tlb_entry_t fetch_slow_path(reg_t addr); |