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authorJerry Zhao <jerryz123@berkeley.edu>2023-12-07 14:20:00 -0800
committerJerry Zhao <jerryz123@berkeley.edu>2023-12-08 18:05:28 -0800
commitae889cb8493a1e31fcbbcb303cf6a7df05fad537 (patch)
tree251b04f6c84f0f36632759695818b60f24aa15ef
parente04f5f321c1ddf2c734d4d52019be3f0ed210d98 (diff)
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Remove cfg_arg_t from cfg_t
Argument parsing should be scoped to the code which constucts cfg_t
-rw-r--r--ci-tests/testlib.c2
-rw-r--r--riscv/cfg.h36
-rw-r--r--riscv/clint.cc2
-rw-r--r--riscv/debug_module.cc6
-rw-r--r--riscv/processor.cc2
-rw-r--r--riscv/sim.cc10
-rw-r--r--spike_main/spike.cc4
7 files changed, 31 insertions, 31 deletions
diff --git a/ci-tests/testlib.c b/ci-tests/testlib.c
index 559a1f8..fff27f4 100644
--- a/ci-tests/testlib.c
+++ b/ci-tests/testlib.c
@@ -43,7 +43,7 @@ int main()
.support_impebreak = true
};
std::vector<std::pair<reg_t, abstract_mem_t*>> mems =
- make_mems(cfg.mem_layout());
+ make_mems(cfg.mem_layout);
sim_t sim(&cfg, false,
mems,
plugin_devices,
diff --git a/riscv/cfg.h b/riscv/cfg.h
index 422c1ae..82d902e 100644
--- a/riscv/cfg.h
+++ b/riscv/cfg.h
@@ -89,24 +89,24 @@ public:
trigger_count(default_trigger_count)
{}
- cfg_arg_t<std::pair<reg_t, reg_t>> initrd_bounds;
- cfg_arg_t<const char *> bootargs;
- cfg_arg_t<const char *> isa;
- cfg_arg_t<const char *> priv;
- cfg_arg_t<const char *> varch;
- bool misaligned;
- endianness_t endianness;
- reg_t pmpregions;
- reg_t pmpgranularity;
- cfg_arg_t<std::vector<mem_cfg_t>> mem_layout;
- std::optional<reg_t> start_pc;
- cfg_arg_t<std::vector<size_t>> hartids;
- bool explicit_hartids;
- cfg_arg_t<bool> real_time_clint;
- reg_t trigger_count;
-
- size_t nprocs() const { return hartids().size(); }
- size_t max_hartid() const { return hartids().back(); }
+ std::pair<reg_t, reg_t> initrd_bounds;
+ const char * bootargs;
+ const char * isa;
+ const char * priv;
+ const char * varch;
+ bool misaligned;
+ endianness_t endianness;
+ reg_t pmpregions;
+ reg_t pmpgranularity;
+ std::vector<mem_cfg_t> mem_layout;
+ std::optional<reg_t> start_pc;
+ std::vector<size_t> hartids;
+ bool explicit_hartids;
+ bool real_time_clint;
+ reg_t trigger_count;
+
+ size_t nprocs() const { return hartids.size(); }
+ size_t max_hartid() const { return hartids.back(); }
};
#endif
diff --git a/riscv/clint.cc b/riscv/clint.cc
index 2fb9ef3..7e7e89c 100644
--- a/riscv/clint.cc
+++ b/riscv/clint.cc
@@ -121,7 +121,7 @@ clint_t* clint_parse_from_fdt(const void* fdt, const sim_t* sim, reg_t* base,
if (fdt_parse_clint(fdt, base, "riscv,clint0") == 0)
return new clint_t(sim,
sim->CPU_HZ / sim->INSNS_PER_RTC_TICK,
- sim->get_cfg().real_time_clint());
+ sim->get_cfg().real_time_clint);
else
return nullptr;
}
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 07723c5..5d49605 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -514,7 +514,7 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
unsigned base = hawindowsel * 32;
for (unsigned i = 0; i < 32; i++) {
unsigned n = base + i;
- if (n < sim->get_cfg().nprocs() && hart_array_mask[sim->get_cfg().hartids()[n]]) {
+ if (n < sim->get_cfg().nprocs() && hart_array_mask[sim->get_cfg().hartids[n]]) {
result |= 1 << i;
}
}
@@ -916,7 +916,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
for (unsigned i = 0; i < 32; i++) {
unsigned n = base + i;
if (n < sim->get_cfg().nprocs()) {
- hart_array_mask[sim->get_cfg().hartids()[n]] = (value >> i) & 1;
+ hart_array_mask[sim->get_cfg().hartids[n]] = (value >> i) & 1;
}
}
}
@@ -1030,5 +1030,5 @@ hart_debug_state_t& debug_module_t::selected_hart_state()
size_t debug_module_t::selected_hart_id() const
{
- return sim->get_cfg().hartids().at(dmcontrol.hartsel);
+ return sim->get_cfg().hartids.at(dmcontrol.hartsel);
}
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5a43d56..1bb1fc9 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -54,7 +54,7 @@ processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg,
}
#endif
- parse_varch_string(cfg->varch());
+ parse_varch_string(cfg->varch);
register_base_instructions();
mmu = new mmu_t(sim, cfg->endianness, this);
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 639c68d..57e9630 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -46,7 +46,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
bool socket_enabled,
FILE *cmd_file) // needed for command line option --cmd
: htif_t(args),
- isa(cfg->isa(), cfg->priv()),
+ isa(cfg->isa, cfg->priv),
cfg(cfg),
mems(mems),
procs(std::max(cfg->nprocs(), size_t(1))),
@@ -99,9 +99,9 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
debug_mmu = new mmu_t(this, cfg->endianness, NULL);
for (size_t i = 0; i < cfg->nprocs(); i++) {
- procs[i] = new processor_t(&isa, cfg, this, cfg->hartids()[i], halted,
+ procs[i] = new processor_t(&isa, cfg, this, cfg->hartids[i], halted,
log_file.get(), sout_);
- harts[cfg->hartids()[i]] = procs[i];
+ harts[cfg->hartids[i]] = procs[i];
}
// When running without using a dtb, skip the fdt-based configuration steps
@@ -134,13 +134,13 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
strstream << fin.rdbuf();
dtb = strstream.str();
} else {
- std::pair<reg_t, reg_t> initrd_bounds = cfg->initrd_bounds();
+ std::pair<reg_t, reg_t> initrd_bounds = cfg->initrd_bounds;
std::string device_nodes;
for (const device_factory_t *factory : device_factories)
device_nodes.append(factory->generate_dts(this));
dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ,
initrd_bounds.first, initrd_bounds.second,
- cfg->bootargs(), cfg->pmpregions, cfg->pmpgranularity,
+ cfg->bootargs, cfg->pmpregions, cfg->pmpgranularity,
procs, mems, device_nodes);
dtb = dts_compile(dts);
}
diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 5376ab9..3bb1c10 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -493,10 +493,10 @@ int main(int argc, char** argv)
help();
std::vector<std::pair<reg_t, abstract_mem_t*>> mems =
- make_mems(cfg.mem_layout());
+ make_mems(cfg.mem_layout);
if (kernel && check_file_exists(kernel)) {
- const char *isa = cfg.isa();
+ const char *isa = cfg.isa;
kernel_size = get_file_size(kernel);
if (isa[2] == '6' && isa[3] == '4')
kernel_offset = 0x200000;