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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-09 19:27:20 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-09 19:27:20 -0800 |
| commit | f5bdc2e34299e3721c9319ba92dc72149f6af8a2 (patch) | |
| tree | 8840695dd11b3fb5ae548905338b07d3873167e4 | |
| parent | f87cdfec1dd79afdabccc848e730d780589b8a65 (diff) | |
| download | riscv-isa-sim-f5bdc2e34299e3721c9319ba92dc72149f6af8a2.zip riscv-isa-sim-f5bdc2e34299e3721c9319ba92dc72149f6af8a2.tar.gz riscv-isa-sim-f5bdc2e34299e3721c9319ba92dc72149f6af8a2.tar.bz2 | |
Remove redundant U/S mode advertisement
| -rw-r--r-- | riscv/processor.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f177090..2dd2749 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -112,10 +112,6 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && max_xlen < 64) bad_isa_string(str); - // advertise support for supervisor and user modes - isa |= 1L << ('s' - 'a'); - isa |= 1L << ('u' - 'a'); - max_isa = isa; } |