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author | Tim Newsome <tim@sifive.com> | 2017-08-10 13:44:42 -0700 |
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committer | GitHub <noreply@github.com> | 2017-08-10 13:44:42 -0700 |
commit | 96218b1cdc0cd395d150e7db08a1b84ea1ae1543 (patch) | |
tree | 75407b6379802c0437771f1df1a7acff28505d02 | |
parent | a327416eac285f50dcbb04e8ddf89204c66ece02 (diff) | |
parent | 4f8b6a69484bd901f213d9a73ea29d26c8022dfd (diff) | |
download | riscv-isa-sim-96218b1cdc0cd395d150e7db08a1b84ea1ae1543.zip riscv-isa-sim-96218b1cdc0cd395d150e7db08a1b84ea1ae1543.tar.gz riscv-isa-sim-96218b1cdc0cd395d150e7db08a1b84ea1ae1543.tar.bz2 |
Merge pull request #117 from riscv/multicore_debug
Fix multicore debug.
-rw-r--r-- | riscv/debug_module.cc | 20 | ||||
-rw-r--r-- | riscv/processor.cc | 4 | ||||
-rw-r--r-- | riscv/processor.h | 6 |
3 files changed, 12 insertions, 18 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 079ebd4..d828b72 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -39,7 +39,7 @@ debug_module_t::debug_module_t(sim_t *sim) : sim(sim) jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO)); memset(debug_abstract, 0, sizeof(debug_abstract)); - + } void debug_module_t::reset() @@ -96,7 +96,7 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) memcpy(bytes, dmdata + addr - debug_data_start, len); return true; } - + if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) { memcpy(bytes, program_buffer + addr - debug_progbuf_start, len); return true; @@ -119,16 +119,16 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) } addr = DEBUG_START + addr; - + if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { memcpy(dmdata + addr - debug_data_start, bytes, len); return true; } - + if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) { fprintf(stderr, "Successful write to program buffer %d bytes at %x\n", (int) len, (int) addr); memcpy(program_buffer + addr - debug_progbuf_start, bytes, len); - + return true; } @@ -276,7 +276,7 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) } else { dmstatus.allresumeack = false; } - + result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning); @@ -381,7 +381,7 @@ bool debug_module_t::perform_abstract_command() //NOP write32(debug_abstract, 0, addi(ZERO, ZERO, 0)); } - + if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) { // Since the next instruction is what we will use, just use nother NOP // to get there. @@ -391,7 +391,7 @@ bool debug_module_t::perform_abstract_command() } debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO; - + abstractcs.busy = true; } else { abstractcs.cmderr = CMDERR_NOTSUP; @@ -418,7 +418,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) } else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) { unsigned i = address - DMI_PROGBUF0; - + if (!abstractcs.busy) write32(program_buffer, i, value); @@ -426,7 +426,7 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) perform_abstract_command(); } return true; - + } else { switch (address) { case DMI_DMCONTROL: diff --git a/riscv/processor.cc b/riscv/processor.cc index 1e3573d..00eccc8 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -202,7 +202,7 @@ void processor_t::enter_debug_mode(uint8_t cause) state.dcsr.prv = state.prv; set_privilege(PRV_M); state.dpc = state.pc; - state.pc = debug_rom_entry(); + state.pc = DEBUG_ROM_ENTRY; } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -217,7 +217,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) if (state.dcsr.cause) { if (t.cause() == CAUSE_BREAKPOINT) { - state.pc = debug_rom_entry(); + state.pc = DEBUG_ROM_ENTRY; } else { state.pc = DEBUG_ROM_TVEC; } diff --git a/riscv/processor.h b/riscv/processor.h index 071f458..6e8d684 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -194,12 +194,6 @@ public: bool slow_path(); bool halted() { return state.dcsr.cause ? true : false; } bool halt_request; - // The unique debug rom address that this hart jumps to when entering debug - // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive. - uint32_t debug_rom_entry() { - fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id); - return DEBUG_ROM_ENTRY + 4 * id; - } // Return the index of a trigger that matched, or -1. inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data) |