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author | Gleb Gagarin <gleb@sifive.com> | 2017-11-15 15:35:59 -0800 |
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committer | Gleb Gagarin <gleb@sifive.com> | 2017-11-15 15:35:59 -0800 |
commit | 85efaaaba8938a7026d5d9203c09e8be0fd66130 (patch) | |
tree | c564ab3594cb2e461a0fd409dcaccd5349ff2d20 | |
parent | 3151df24e57d9a9148ad3ca6f856e33c2894a48e (diff) | |
download | riscv-isa-sim-85efaaaba8938a7026d5d9203c09e8be0fd66130.zip riscv-isa-sim-85efaaaba8938a7026d5d9203c09e8be0fd66130.tar.gz riscv-isa-sim-85efaaaba8938a7026d5d9203c09e8be0fd66130.tar.bz2 |
Support for non-contiguous hartids
-rw-r--r-- | riscv/sim.cc | 17 | ||||
-rw-r--r-- | riscv/sim.h | 2 | ||||
-rw-r--r-- | spike_main/spike.cc | 16 |
3 files changed, 30 insertions, 5 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 647cc46..57ba857 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -25,7 +25,7 @@ static void handle_signal(int sig) sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, - const std::vector<std::string>& args) + const std::vector<std::string>& args, std::vector<int> const hartids) : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))), start_pc(start_pc), current_step(0), current_proc(0), debug(false), remote_bitbang(NULL) @@ -39,8 +39,19 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, debug_mmu = new mmu_t(this, NULL); - for (size_t i = 0; i < procs.size(); i++) { - procs[i] = new processor_t(isa, this, i, halted); + if (hartids.size() == 0) { + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, i, halted); + } + } + else { + if (hartids.size() != procs.size()) { + std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl; + exit(1); + } + for (size_t i = 0; i < procs.size(); i++) { + procs[i] = new processor_t(isa, this, hartids[i], halted); + } } clint.reset(new clint_t(procs)); diff --git a/riscv/sim.h b/riscv/sim.h index 9372cc1..b102a6b 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -21,7 +21,7 @@ class sim_t : public htif_t public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, - const std::vector<std::string>& args); + const std::vector<std::string>& args, const std::vector<int> hartids); ~sim_t(); // run the simulation to completion diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 23f8e49..3061b10 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -84,6 +84,19 @@ int main(int argc, char** argv) const char* isa = DEFAULT_ISA; uint16_t rbb_port = 0; bool use_rbb = false; + std::vector<int> hartids; + + auto const hartids_parser = [&](const char *s) { + std::string const str(s); + std::stringstream stream(str); + + int n; + while (stream >> n) + { + hartids.push_back(n); + if (stream.peek() == ',') stream.ignore(); + } + }; option_parser_t parser; parser.help(&help); @@ -97,6 +110,7 @@ int main(int argc, char** argv) parser.option('H', 0, 0, [&](const char* s){halted = true;}); parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoi(s);}); parser.option(0, "pc", 1, [&](const char* s){start_pc = strtoull(s, 0, 0);}); + parser.option(0, "hartids", 1, hartids_parser); parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));}); parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));}); parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));}); @@ -116,7 +130,7 @@ int main(int argc, char** argv) if (mems.empty()) mems = make_mems("2048"); - sim_t s(isa, nprocs, halted, start_pc, mems, htif_args); + sim_t s(isa, nprocs, halted, start_pc, mems, htif_args, std::move(hartids)); std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL); std::unique_ptr<jtag_dtm_t> jtag_dtm(new jtag_dtm_t(&s.debug_module)); if (use_rbb) { |