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| author | Andrew Waterman <andrew@sifive.com> | 2023-08-23 23:28:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-08-23 23:28:40 -0700 |
| commit | db20475248147ffe2c25fdfccc3284de4cae45fa (patch) | |
| tree | 131d10714c96ee132614d788de60f3b08148dc08 | |
| parent | d1680b75debfdb09905d08cdf0cd8104449ddb21 (diff) | |
| parent | 179951a01540af002ddc1827521f89c997c97374 (diff) | |
| download | riscv-isa-sim-db20475248147ffe2c25fdfccc3284de4cae45fa.zip riscv-isa-sim-db20475248147ffe2c25fdfccc3284de4cae45fa.tar.gz riscv-isa-sim-db20475248147ffe2c25fdfccc3284de4cae45fa.tar.bz2 | |
Merge pull request #1434 from dansmathers/master
update model_test.h: set_msw/clear_msw/set_mtimer/clear_mtimer
| -rw-r--r-- | arch_test_target/spike/model_test.h | 50 |
1 files changed, 42 insertions, 8 deletions
diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h index e968e43..bfdb442 100644 --- a/arch_test_target/spike/model_test.h +++ b/arch_test_target/spike/model_test.h @@ -49,16 +49,50 @@ //RVTEST_IO_ASSERT_DFPR_EQ
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
-#define RVMODEL_SET_MSW_INT \
- li t1, 1; \
- li t2, 0x2000000; \
- sw t1, 0(t2);
+#ifndef RVMODEL_MCLINTBASE
+ #define RVMODEL_MCLINTBASE 0x02000000
+#endif
+
+#ifndef RVMODEL_MSIP_OFFSET
+ #define RVMODEL_MSIP_OFFSET 0x0
+#endif
+
+#ifndef RVMODEL_MTIMECMP_OFFSET
+ #define RVMODEL_MTIMECMP_OFFSET 0x4000
+#endif
+
+#ifndef RVMODEL_MTIMECMPH_OFFSET
+ #define RVMODEL_MTIMECMPH_OFFSET 0x4004
+#endif
+
+#define RVMODEL_SET_MSW_INT \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \
+ li t1, 1; \
+ sw t1, (t0); \
+
+#define RVMODEL_CLEAR_MSW_INT \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \
+ sw x0, (t0); \
-#define RVMODEL_CLEAR_MSW_INT \
- li t2, 0x2000000; \
- sw x0, 0(t2);
+#define RVMODEL_SET_MTIMER_INT \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \
+ sw x0, (t0); \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \
+ sw x0, (t0); \
-#define RVMODEL_CLEAR_MTIMER_INT
+#define RVMODEL_CLEAR_MTIMER_INT \
+ addi t1,x0,1; \
+ neg t1,t1; \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \
+ sw t1, (t0); \
+ lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \
+ addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \
+ sw t1, (t0); \
#define RVMODEL_CLEAR_MEXT_INT
|