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| author | Andrew Waterman <andrew@sifive.com> | 2023-10-10 12:07:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-10 12:07:18 -0700 |
| commit | b5d13f36053d08e310da01e92e8ebc2d29623483 (patch) | |
| tree | 7db35c06ca249c7dfd3bb5e788c57abd207fe39c | |
| parent | d1efcdffffee57bab0fdbd2b377c6132b37556fd (diff) | |
| parent | c5eee7426d7c1eb987544ad03671173d228ca69a (diff) | |
| download | riscv-isa-sim-b5d13f36053d08e310da01e92e8ebc2d29623483.zip riscv-isa-sim-b5d13f36053d08e310da01e92e8ebc2d29623483.tar.gz riscv-isa-sim-b5d13f36053d08e310da01e92e8ebc2d29623483.tar.bz2 | |
Merge pull request #1477 from abejgonzalez/patch-1
Update dtm.h with switch_to_* functions
| -rw-r--r-- | fesvr/dtm.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/fesvr/dtm.h b/fesvr/dtm.h index 1f5ee3e..f47b648 100644 --- a/fesvr/dtm.h +++ b/fesvr/dtm.h @@ -55,6 +55,12 @@ class dtm_t : public htif_t void producer_thread(); + void switch_to_host() { + // update the target with the current context + target = context_t::current(); + host.switch_to(); + } + protected: virtual void read_chunk(addr_t taddr, size_t len, void* dst) override; virtual void write_chunk(addr_t taddr, size_t len, const void* src) override; @@ -74,6 +80,10 @@ class dtm_t : public htif_t void resume(int); uint32_t get_data_base() { return data_base; }; + void switch_to_target() { + target->switch_to(); + } + private: context_t host; context_t* target; |