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| author | Tim Newsome <tim@sifive.com> | 2023-09-28 09:07:56 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-09-28 09:07:56 -0700 |
| commit | 7613da4d26dbaaf9063540187a4a880cb3c0b3e9 (patch) | |
| tree | 2334119ff3934f358ef13a94dd6936c7a1c12713 | |
| parent | 847fe5d59a5e198146eca6a3c69fe96b07dad5c6 (diff) | |
| download | riscv-isa-sim-7613da4d26dbaaf9063540187a4a880cb3c0b3e9.zip riscv-isa-sim-7613da4d26dbaaf9063540187a4a880cb3c0b3e9.tar.gz riscv-isa-sim-7613da4d26dbaaf9063540187a4a880cb3c0b3e9.tar.bz2 | |
debug: Halted harts can also be unavailable.
| -rw-r--r-- | riscv/debug_module.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 4a7a802..026f4b3 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -413,14 +413,14 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) dmstatus.allresumeack = false; } auto hart = sim->get_harts().at(hart_id); - if (hart_state[hart_id].halted) { - dmstatus.allrunning = false; - dmstatus.anyhalted = true; - dmstatus.allunavail = false; - } else if (!hart_available(hart_id)) { + if (!hart_available(hart_id)) { dmstatus.allrunning = false; dmstatus.allhalted = false; dmstatus.anyunavail = true; + } else if (hart_state[hart_id].halted) { + dmstatus.allrunning = false; + dmstatus.anyhalted = true; + dmstatus.allunavail = false; } else { dmstatus.allhalted = false; dmstatus.anyrunning = true; |