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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-06-02 16:39:45 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2023-06-20 12:23:47 -0700 |
| commit | cd0bd1bda701f5004f9667d0c87a8b65f54d30e3 (patch) | |
| tree | 7a515feed4152444b2502add9c44843dd3e885a8 | |
| parent | 1bd44c71a13f3d8d25de112fb5346589c03e332d (diff) | |
| download | riscv-isa-sim-cd0bd1bda701f5004f9667d0c87a8b65f54d30e3.zip riscv-isa-sim-cd0bd1bda701f5004f9667d0c87a8b65f54d30e3.tar.gz riscv-isa-sim-cd0bd1bda701f5004f9667d0c87a8b65f54d30e3.tar.bz2 | |
sim_t: Make static consts public members
| -rw-r--r-- | riscv/sim.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 6e69078..7689d54 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -59,6 +59,10 @@ public: // Callback for processors to let the simulation know they were reset. virtual void proc_reset(unsigned id) override; + static const size_t INTERLEAVE = 5000; + static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU + private: isa_parser_t isa; const cfg_t * const cfg; @@ -82,9 +86,6 @@ private: processor_t* get_core(const std::string& i); void step(size_t n); // step through simulation - static const size_t INTERLEAVE = 5000; - static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core - static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; |