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author | Gianluca Guida <gianluca@rivosinc.com> | 2023-05-25 14:43:57 +0100 |
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committer | Gianluca Guida <gianluca@rivosinc.com> | 2023-05-26 21:34:57 +0100 |
commit | c231e0c9f6dcf3e9fe0637724d8672560d62c58e (patch) | |
tree | eb74966df5fdf0a3bba67ab2ee89ee93cdaaf531 | |
parent | 3010cb4175c5b3f485e6ce7e749afa0667f71dbe (diff) | |
download | riscv-isa-sim-c231e0c9f6dcf3e9fe0637724d8672560d62c58e.zip riscv-isa-sim-c231e0c9f6dcf3e9fe0637724d8672560d62c58e.tar.gz riscv-isa-sim-c231e0c9f6dcf3e9fe0637724d8672560d62c58e.tar.bz2 |
Fix check for extension
Calling 'extension_enabled' this early during the constructor of
'processor_t' causes SIGSEGV.
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e5ae60b..a75b0ff 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -43,7 +43,7 @@ processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg, TM.proc = this; #ifndef HAVE_INT128 - if (extension_enabled('V')) { + if (isa->extension_enabled('V')) { fprintf(stderr, "V extension is not supported on platforms without __int128 type\n"); abort(); } |