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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-02 09:45:17 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-02 09:45:17 -0800 |
| commit | aa10facde0f48d62954cd096508d9c3001110e45 (patch) | |
| tree | 77393d004a2cd6632a5eb8fb31c80ec05e279534 | |
| parent | 1742648305d50c193c53f3356732261e9b83af20 (diff) | |
| parent | 860a120bf16ba32eb491111bdf1b214bfa652654 (diff) | |
| download | riscv-isa-sim-aa10facde0f48d62954cd096508d9c3001110e45.zip riscv-isa-sim-aa10facde0f48d62954cd096508d9c3001110e45.tar.gz riscv-isa-sim-aa10facde0f48d62954cd096508d9c3001110e45.tar.bz2 | |
Merge pull request #1266 from riscv-software-src/fix-o0-compile
Define sim_t::INTERLEAVE so that it can be accessed by reference
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index a31e057..dcbd469 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -30,6 +30,8 @@ static void handle_signal(int sig) signal(sig, &handle_signal); } +const size_t sim_t::INTERLEAVE; + sim_t::sim_t(const cfg_t *cfg, bool halted, std::vector<std::pair<reg_t, mem_t*>> mems, std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices, |