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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 20:16:48 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-24 18:40:56 -0800 |
| commit | a9eae3e6290c1c3b2bcfcce1990b5513a69b6f19 (patch) | |
| tree | d0d9d94894cf0c34ea1a116143be9b2e51c4bd4b | |
| parent | 45b894876112a9f6ac5639bb6ee8427211df7280 (diff) | |
| download | riscv-isa-sim-a9eae3e6290c1c3b2bcfcce1990b5513a69b6f19.zip riscv-isa-sim-a9eae3e6290c1c3b2bcfcce1990b5513a69b6f19.tar.gz riscv-isa-sim-a9eae3e6290c1c3b2bcfcce1990b5513a69b6f19.tar.bz2 | |
rvv: add vsetivli
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | disasm/disasm.cc | 1 | ||||
| -rw-r--r-- | riscv/decode.h | 1 | ||||
| -rw-r--r-- | riscv/encoding.h | 5 | ||||
| -rw-r--r-- | riscv/insns/vsetivli.h | 2 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
5 files changed, 9 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index aee9f5c..ff8bddb 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -800,6 +800,7 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("c.fsd", c_fsd, 0, {&rvc_fp_rs2s, &rvc_ld_address}); DISASM_INSN("c.fsdsp", c_fsdsp, 0, {&rvc_fp_rs2, &rvc_sdsp_address}); + DISASM_INSN("vsetivli", vsetivli, 0, {&xrd, &zimm5, &v_vtype}); DISASM_INSN("vsetvli", vsetvli, 0, {&xrd, &xrs1, &v_vtype}); DISASM_INSN("vsetvl", vsetvl, 0, {&xrd, &xrs1, &xrs2}); diff --git a/riscv/decode.h b/riscv/decode.h index 465b816..591e41d 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -119,6 +119,7 @@ public: uint64_t v_nf() { return x(29, 3); } uint64_t v_simm5() { return xs(15, 5); } uint64_t v_zimm5() { return x(15, 5); } + uint64_t v_zimm10() { return x(20, 10); } uint64_t v_zimm11() { return x(20, 11); } uint64_t v_lmul() { return x(20, 2); } uint64_t v_frac_lmul() { return x(22, 1); } diff --git a/riscv/encoding.h b/riscv/encoding.h index ba5fa21..881ed7d 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in - * https://github.com/riscv/riscv-opcodes (79c18f0) + * https://github.com/riscv/riscv-opcodes (e8f0392) */ /* See LICENSE for license details. */ @@ -1222,6 +1222,8 @@ #define MASK_CUSTOM3_RD_RS1 0x707f #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b #define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define MATCH_VSETIVLI 0xc0007057 +#define MASK_VSETIVLI 0xc000707f #define MATCH_VSETVLI 0x7057 #define MASK_VSETVLI 0x8000707f #define MATCH_VSETVL 0x80007057 @@ -2891,6 +2893,7 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V) diff --git a/riscv/insns/vsetivli.h b/riscv/insns/vsetivli.h new file mode 100644 index 0000000..04900a2 --- /dev/null +++ b/riscv/insns/vsetivli.h @@ -0,0 +1,2 @@ +require_vector_novtype(false, false); +WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 0a25b0a..d4422fe 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -875,6 +875,7 @@ riscv_insn_ext_v_ldst = \ vs8r_v \ riscv_insn_ext_v_ctrl = \ + vsetivli \ vsetvli \ vsetvl \ |