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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-03-27 10:29:37 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2023-03-27 18:24:22 -0700 |
| commit | 384316fb36dd382120fe2b3e6ffe91a2c1e0bbee (patch) | |
| tree | 9439c2997e7d05ccec93a1606c7d8b727082fa02 | |
| parent | 5e366af7735a69f4066f285c91fea068665d52be (diff) | |
| download | riscv-isa-sim-384316fb36dd382120fe2b3e6ffe91a2c1e0bbee.zip riscv-isa-sim-384316fb36dd382120fe2b3e6ffe91a2c1e0bbee.tar.gz riscv-isa-sim-384316fb36dd382120fe2b3e6ffe91a2c1e0bbee.tar.bz2 | |
Add zicntr_zihpm to DEFAULT_ISA
| -rwxr-xr-x | configure | 5 | ||||
| -rw-r--r-- | riscv/riscv.ac | 4 |
2 files changed, 5 insertions, 4 deletions
@@ -1381,7 +1381,8 @@ Optional Packages: use the Regex library from boost - it is possible to specify a certain library for the linker e.g. --with-boost-regex=boost_regex-gcc-mt-d-1_33_1 - --with-isa=RV64IMAFDC Sets the default RISC-V ISA + --with-isa=RV64IMAFDC_zicntr_zihpm + Sets the default RISC-V ISA --with-priv=MSU Sets the default RISC-V privilege modes supported --with-varch=vlen:128,elen:64 Sets the default vector config @@ -5876,7 +5877,7 @@ _ACEOF else cat >>confdefs.h <<_ACEOF -#define DEFAULT_ISA "RV64IMAFDC" +#define DEFAULT_ISA "RV64IMAFDC_zicntr_zihpm" _ACEOF fi diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 0b879db..e52c570 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -9,10 +9,10 @@ AC_CHECK_LIB([boost_system], [main], [], []) AC_CHECK_LIB([boost_regex], [main], [], []) AC_ARG_WITH(isa, - [AS_HELP_STRING([--with-isa=RV64IMAFDC], + [AS_HELP_STRING([--with-isa=RV64IMAFDC_zicntr_zihpm], [Sets the default RISC-V ISA])], AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]), - AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC", [Default value for --isa switch])) + AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC_zicntr_zihpm", [Default value for --isa switch])) AC_ARG_WITH(priv, [AS_HELP_STRING([--with-priv=MSU], |