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| author | Andrew Waterman <andrew@sifive.com> | 2023-03-01 13:05:10 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-03-01 13:34:07 -0800 |
| commit | 2ec72f2a84d77ac43044bf5593923468990d1b40 (patch) | |
| tree | ae110c9eda0801bff65732b0900ee4336d57fc07 | |
| parent | ef1638be6cdb6cfb77d77f5ae233e5e196e40125 (diff) | |
| download | riscv-isa-sim-2ec72f2a84d77ac43044bf5593923468990d1b40.zip riscv-isa-sim-2ec72f2a84d77ac43044bf5593923468990d1b40.tar.gz riscv-isa-sim-2ec72f2a84d77ac43044bf5593923468990d1b40.tar.bz2 | |
Remove unnecessary conditional in plic_t::load
It's safe to overwrite bytes when returning false.
| -rw-r--r-- | riscv/plic.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/plic.cc b/riscv/plic.cc index 5aa0923..57355ef 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -329,9 +329,7 @@ bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes) } } - if (ret) { - memcpy(bytes, (uint8_t *)&val, len); - } + memcpy(bytes, (uint8_t *)&val, len); return ret; } |