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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-10-18 17:17:18 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-10-18 17:17:18 -0700 |
| commit | 4f3f70f6b7a115ddb159953df5f5cb4261260685 (patch) | |
| tree | 16bb2b5e7de67846005f63e312975067628bf4ea | |
| parent | 4ddd7773f8fb40ea1c9b48c8f3a61a40c3f168fb (diff) | |
| download | riscv-isa-sim-4f3f70f6b7a115ddb159953df5f5cb4261260685.zip riscv-isa-sim-4f3f70f6b7a115ddb159953df5f5cb4261260685.tar.gz riscv-isa-sim-4f3f70f6b7a115ddb159953df5f5cb4261260685.tar.bz2 | |
fix vf
| -rw-r--r-- | riscv/insns/vf.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h index 7779645..d1527b3 100644 --- a/riscv/insns/vf.h +++ b/riscv/insns/vf.h @@ -3,6 +3,7 @@ for (int i=0; i<VL; i++) { uts[i]->pc = RS1+SIMM; uts[i]->utmode = true; + uts[i]->run = true; while (uts[i]->utmode) uts[i]->step(1, false); // XXX } |