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| author | Andrew Waterman <andrew@sifive.com> | 2023-07-07 13:59:04 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-07 13:59:04 -0700 |
| commit | ed5dccb2911f3b2dda731e5fe65e6c03ad0b46fb (patch) | |
| tree | a11276636d78a3553b7ac8663ae4368133d3d43e | |
| parent | e9848ed3056eba91a5f0d15539358e5a03c66011 (diff) | |
| parent | 37bef605d5ac2a92151725f10c1e53b86818aa55 (diff) | |
| download | riscv-isa-sim-ed5dccb2911f3b2dda731e5fe65e6c03ad0b46fb.zip riscv-isa-sim-ed5dccb2911f3b2dda731e5fe65e6c03ad0b46fb.tar.gz riscv-isa-sim-ed5dccb2911f3b2dda731e5fe65e6c03ad0b46fb.tar.bz2 | |
Merge pull request #1402 from riscv-software-src/zicond-default-disasm
Disassemble Zicond by default
| -rw-r--r-- | disasm/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 6f93d24..b2bed47 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2329,7 +2329,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zkn_zkr_zks_svinval"; + "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zicond_zkn_zkr_zks_svinval"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); |