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| author | Andrew Waterman <andrew@sifive.com> | 2023-11-30 17:26:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-30 17:26:03 -0800 |
| commit | d74ab37106c4318c75f1c63df86cec15254c7268 (patch) | |
| tree | 69e1bd3b667f071a24d57e54624dac9d0b98face | |
| parent | 0c1397661ce383fa303bd878b2fc1172f3ad9213 (diff) | |
| parent | e9ae2287e174b67df95556266647731125307989 (diff) | |
| download | riscv-isa-sim-d74ab37106c4318c75f1c63df86cec15254c7268.zip riscv-isa-sim-d74ab37106c4318c75f1c63df86cec15254c7268.tar.gz riscv-isa-sim-d74ab37106c4318c75f1c63df86cec15254c7268.tar.bz2 | |
Merge pull request #1517 from YenHaoChen/patch-1
typo: vwsll.vi: fix a typo on disassembling vwsll.vi
| -rw-r--r-- | disasm/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 6917fa5..ad48ea8 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2249,7 +2249,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) #define DISASM_VECTOR_VV_VX_VIU(name) \ DEFINE_VECTOR_VV(name##_vv); \ DEFINE_VECTOR_VX(name##_vx); \ - DEFINE_VECTOR_VIU(name##_vx) + DEFINE_VECTOR_VIU(name##_vi) #define DISASM_VECTOR_VV_VX_VIU_ZIMM6(name) \ DEFINE_VECTOR_VV(name##_vv); \ DEFINE_VECTOR_VX(name##_vx); \ |