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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-19 11:45:23 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-19 11:45:23 -0700 |
| commit | 93f1d11a4f8bb6b00bbd6528684076f29afbcef1 (patch) | |
| tree | 663dfba3e0287655eb4c6b692d4ef4dbfc80efd8 | |
| parent | f8ca42bf489e9cad95a1df27fc405b5d1d8c23ec (diff) | |
| download | riscv-isa-sim-93f1d11a4f8bb6b00bbd6528684076f29afbcef1.zip riscv-isa-sim-93f1d11a4f8bb6b00bbd6528684076f29afbcef1.tar.gz riscv-isa-sim-93f1d11a4f8bb6b00bbd6528684076f29afbcef1.tar.bz2 | |
[sim] change default hwvl
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3548810..0bab83a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -37,11 +37,11 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz) vecbanks = 0xff; vecbanks_count = 8; utidx = -1; - vlmax = 8; + vlmax = 32; vl = 0; nxfpr_bank = 256; - nxpr_use = 0; - nfpr_use = 0; + nxpr_use = 32; + nfpr_use = 32; for (int i=0; i<MAX_UTS; i++) uts[i] = NULL; |