From ef9f02e7fba47412d6c057ba78fd3d89cb4e5fc3 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Fri, 14 Oct 2022 08:32:46 +0800 Subject: lib: utils/timer: Add Andes fdt timer support Since we can get the PLMT base address and timer frequency from device tree, move plmt timer device to fdt timer framework. dts example (Quad-core AX45MP): cpus { ... timebase-frequency = <0x3938700>; ... } soc { ... plmt0@e6000000 { compatible = "andestech,plmt0"; reg = <0x00 0xe6000000 0x00 0x100000>; interrupts-extended = <&cpu0_intc 0x07 &cpu1_intc 0x07 &cpu2_intc 0x07 &cpu3_intc 0x07>; }; ... } Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel --- include/sbi_utils/timer/andes_plmt.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/sbi_utils/timer/andes_plmt.h (limited to 'include/sbi_utils/timer') diff --git a/include/sbi_utils/timer/andes_plmt.h b/include/sbi_utils/timer/andes_plmt.h new file mode 100644 index 00000000..08bce332 --- /dev/null +++ b/include/sbi_utils/timer/andes_plmt.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2022 Andes Technology Corporation + * + * Authors: + * Zong Li + * Nylon Chen + * Yu Chien Peter Lin + */ + +#ifndef __TIMER_ANDES_PLMT_H__ +#define __TIMER_ANDES_PLMT_H__ + +#define DEFAULT_AE350_PLMT_FREQ 60000000 +#define PLMT_REGION_ALIGN 0x1000 + +struct plmt_data { + u32 hart_count; + unsigned long size; + unsigned long timer_freq; + volatile u64 *time_val; + volatile u64 *time_cmp; +}; + +int plmt_cold_timer_init(struct plmt_data *plmt); +int plmt_warm_timer_init(void); + +#endif /* __TIMER_ANDES_PLMT_H__ */ -- cgit v1.2.3