let vm_sv32 and vm_sv39 depend on S-mode (#674) (#683)HEADdev

Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>

70 files changed, 70 insertions, 70 deletions

diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S
index 3c9f330..abc8951 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S
index 1737706..2552d0c 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S
index 4258538..5654c9d 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S
index c079820..9868f42 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S
index 28c8b22..9dfb204 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S
index c552054..e7ab13a 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S
@@ -38,7 +38,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", satp_access_all_modes)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", satp_access_all_modes)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S
index b0ffeab..165d63e 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S
@@ -72,7 +72,7 @@ RVTEST_CODE_BEGIN
 */
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def SOFTWARE_UPDATE_A_D=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def SOFTWARE_UPDATE_A_D=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 // ------------------------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S
index 6ec4ef4..4a2724c 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S
@@ -70,7 +70,7 @@ RVTEST_CODE_BEGIN
 */
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;  def SOFTWARE_UPDATE_A_D=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;  def SOFTWARE_UPDATE_A_D=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 // ------------------------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S
index 1316f88..073d121 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S
@@ -52,7 +52,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_set_in_UMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_set_in_UMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S
index 3dd17d3..e1fd782 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S
@@ -52,7 +52,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_unset_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_unset_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S
index e67ce9a..d2b2e34 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S
@@ -62,7 +62,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", U_bit_unset_in_UMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", U_bit_unset_in_UMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S
index f09be62..73bad75 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S
@@ -20,7 +20,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", VA_all_ones)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", VA_all_ones)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S
index 8f5d025..01cf90d 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S
@@ -26,7 +26,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", global_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", global_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S
index dce5a48..e107bf4 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S
@@ -26,7 +26,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", global_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", global_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S
index 8182e5e..1a1184c 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S
@@ -37,7 +37,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S
index 7a51365..8758126 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S
@@ -38,7 +38,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S
index b8df0ee..a97945e 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S
@@ -32,7 +32,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S
index 5d366bc..5d990f8 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S
@@ -32,7 +32,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S
index 5b5c630..efdca4c 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S
@@ -36,7 +36,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S
index 6e124b7..1b66e51 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S
@@ -36,7 +36,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S
index 7ffba23..4a1edb1 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S
@@ -39,7 +39,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S
index 127f077..63da1d8 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S
@@ -39,7 +39,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S
index 899abda..5b1d5bd 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S
@@ -23,7 +23,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_set_bare_mode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_set_bare_mode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S
index 08a740c..0ea3b8c 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S
@@ -23,7 +23,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",mstatus_sbe_set)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",mstatus_sbe_set)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S
index 4375b39..bcd91a9 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S
@@ -23,7 +23,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",mstatus_sbe_set)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",mstatus_sbe_set)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S
index bd61564..4e75f93 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S
@@ -40,7 +40,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S
index b646b63..cdb3512 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S
@@ -40,7 +40,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S
index 83e43f7..5fc6d89 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S
@@ -32,7 +32,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S
index eaf8bf5..910d769 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S
@@ -32,7 +32,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S
index aa34dd8..66974b7 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S
@@ -42,7 +42,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S
index f6ed56d..9bcd197 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S
@@ -42,7 +42,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S
index f64b55a..e79eede 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S
@@ -38,7 +38,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S
index 96ac761..00e4a9b 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S
@@ -38,7 +38,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S
index 7ba5a32..4aca8cd 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S
@@ -62,7 +62,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_sum_set_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_sum_set_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S
index 38896e5..cc91228 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S
@@ -31,7 +31,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", sum_set_U_bit_unset_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", sum_set_U_bit_unset_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S
index 9227af0..eca0ec4 100644
--- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S
+++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S
@@ -52,7 +52,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_no_sum_set_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_no_sum_set_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_S_mode.S
index b4b22d8..62b53df 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_S_mode.S
@@ -95,7 +95,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_U_mode.S
index eadb429..a0d75cc 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_A_and_D_U_mode.S
@@ -95,7 +95,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_VA_all_ones_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_VA_all_ones_S_mode.S
index 4a7f57d..b0cb58e 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_VA_all_ones_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_VA_all_ones_S_mode.S
@@ -28,7 +28,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_S_mode.S
index 8ce5a4e..0d938b4 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_S_mode.S
@@ -56,7 +56,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_U_mode.S
index 385b1fb..fbda8e7 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_canonical_U_mode.S
@@ -56,7 +56,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_S_mode.S
index 0943323..660ba1a 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_S_mode.S
@@ -55,7 +55,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",invalid_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",invalid_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_U_mode.S
index 0664ab4..505ae58 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_invalid_pte_U_mode.S
@@ -55,7 +55,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",invalid_pte)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",invalid_pte)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_S_mode.S
index 5f3a72e..4cb6cd4 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_S_mode.S
@@ -30,7 +30,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_U_mode.S
index 1433401..79d70e8 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_misaligned_U_mode.S
@@ -30,7 +30,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_S_mode.S
index a4e9492..ad08dbe 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_S_mode.S
@@ -58,7 +58,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_mode.S
index 27a8fc6..3294ac8 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_mode.S
@@ -59,7 +59,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_set_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_set_S_mode.S
index 0d57520..2a5e7db 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_set_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_set_S_mode.S
@@ -58,7 +58,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_unset_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_unset_S_mode.S
index 36d48aa..b31f65b 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_unset_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_U_set_sum_unset_S_mode.S
@@ -58,7 +58,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_bare_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_bare_mode.S
index 1b667a8..b5ff610 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_bare_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mprv_bare_mode.S
@@ -30,7 +30,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_S_mode.S
index 2ffc809..6aae440 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_S_mode.S
@@ -58,7 +58,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_sum_set_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_sum_set_S_mode.S
index 2baab9d..62ab54e 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_sum_set_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_sbe_set_sum_set_S_mode.S
@@ -58,7 +58,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_tvm_test.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_tvm_test.S
index ce4ef12..c313386 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_tvm_test.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mstatus_tvm_test.S
@@ -31,7 +31,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_S_mode.S
index 9ae053e..1bbc265 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_S_mode.S
@@ -61,7 +61,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",MXR_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",MXR_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_U_mode.S
index addc765..7f6bf3a 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_mxr_U_mode.S
@@ -61,7 +61,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",MXR_bit)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",MXR_bit)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_S_mode.S
index 300e9fa..371f233 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_S_mode.S
@@ -51,7 +51,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",nonleaf_pte_level0)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",nonleaf_pte_level0)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_U_mode.S
index 8b0b707..769ff9d 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_nleaf_pte_level0_U_mode.S
@@ -51,7 +51,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",nonleaf_pte_level0)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",nonleaf_pte_level0)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_S_mode.S
index 3e250b6..c936290 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_S_mode.S
@@ -61,7 +61,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_U_mode.S
index 15eb436..9c60a5f 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_res_global_pte_U_mode.S
@@ -61,7 +61,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",sv39_template)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_S_mode.S
index cd6659c..78efe02 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_S_mode.S
@@ -67,7 +67,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rsw_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rsw_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_U_mode.S
index ca889c5..e415b15 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rsw_pte_U_mode.S
@@ -67,7 +67,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rsw_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rsw_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_S_mode.S
index 5b3eb67..9c50322 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_S_mode.S
@@ -62,7 +62,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_U_mode.S
index 854ad70..c3cc079 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_rwx_pte_U_mode.S
@@ -62,7 +62,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S
index 7b8f6db..12ed111 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S
@@ -53,7 +53,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S
index 2e85fa9..ab5c8cd 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S
@@ -55,7 +55,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_satp_access_tests.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_satp_access_tests.S
index 58ef8c8..2b1dc25 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_satp_access_tests.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_satp_access_tests.S
@@ -30,7 +30,7 @@ rvtest_entry_point:
 RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",satp_access_all_modes)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",satp_access_all_modes)
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
 
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_spage_access_U_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_spage_access_U_mode.S
index 5552981..1a9755d 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_spage_access_U_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_spage_access_U_mode.S
@@ -56,7 +56,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",reserved_rwx_pte_perm)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_S_mode.S
index 94fb85f..1efde08 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_S_mode.S
@@ -83,7 +83,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_sum_set_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_sum_set_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_U_bit_unset_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_U_bit_unset_S_mode.S
index fb3e321..3b78483 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_U_bit_unset_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_set_U_bit_unset_S_mode.S
@@ -70,7 +70,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_sum_set_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_sum_set_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------
diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_unset_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_unset_S_mode.S
index e3e9bb6..5bbf1a1 100644
--- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_unset_S_mode.S
+++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_sum_unset_S_mode.S
@@ -82,7 +82,7 @@ starting_point:
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_no_sum_set_in_SMode)
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",U_bit_no_sum_set_in_SMode)
 
 RVTEST_SIGBASE( x13,signature_x13_1)
 # ---------------------------------------------------------------------------------------------