From 2c9a83235282c11b197278cd9c072e96c58b2429 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Oct 2010 19:41:39 -0700 Subject: [sim,xcc,pk,opcodes] static rounding modes for FP insns Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.) --- riscv/decode.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/decode.h') diff --git a/riscv/decode.h b/riscv/decode.h index 810af3f..3db82da 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -175,6 +175,7 @@ private: #define TARGET insn.jtype.target #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS)) #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS)) +#define RM ((insn.ftype.ffunct >> 1) & 3) #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction #define require64 if(gprlen != 64) throw trap_illegal_instruction -- cgit v1.1