From 27ffc270f4e08862606e3532a87556e2f16fa87b Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 19 Oct 2017 12:18:23 -0700
Subject: Fix implementation of FMIN/FMAX NaN case

If rd=rs1 or rd=rs2, the NaN check examined the wrong value.
---
 riscv/insns/fmax_d.h | 3 ++-
 riscv/insns/fmax_q.h | 3 ++-
 riscv/insns/fmax_s.h | 3 ++-
 riscv/insns/fmin_d.h | 3 ++-
 riscv/insns/fmin_q.h | 3 ++-
 riscv/insns/fmin_s.h | 3 ++-
 6 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 3d2c6e6..11491f5 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -2,7 +2,8 @@ require_extension('D');
 require_fp;
 bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
                (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
-WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
   WRITE_FRD(f64(defaultNaNF64UI));
+else
+  WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_q.h b/riscv/insns/fmax_q.h
index 719e6d0..7dd7884 100644
--- a/riscv/insns/fmax_q.h
+++ b/riscv/insns/fmax_q.h
@@ -2,7 +2,8 @@ require_extension('Q');
 require_fp;
 bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) ||
                (f128_eq(f128(FRS2), f128(FRS1)) && (f128(FRS2).v[1] & F64_SIGN));
-WRITE_FRD(greater || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2)))
   WRITE_FRD(f128(defaultNaNF128()));
+else
+  WRITE_FRD(greater || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 33e535b..41d8f92 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -2,7 +2,8 @@ require_extension('F');
 require_fp;
 bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
                (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
-WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
   WRITE_FRD(f32(defaultNaNF32UI));
+else
+  WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 486faa5..5cf349d 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -2,7 +2,8 @@ require_extension('D');
 require_fp;
 bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
             (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
-WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
   WRITE_FRD(f64(defaultNaNF64UI));
+else
+  WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_q.h b/riscv/insns/fmin_q.h
index 675c7fd..fcb9526 100644
--- a/riscv/insns/fmin_q.h
+++ b/riscv/insns/fmin_q.h
@@ -2,7 +2,8 @@ require_extension('Q');
 require_fp;
 bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) ||
             (f128_eq(f128(FRS1), f128(FRS2)) && (f128(FRS1).v[1] & F64_SIGN));
-WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2)))
   WRITE_FRD(f128(defaultNaNF128()));
+else
+  WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 8099003..19e1193 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -2,7 +2,8 @@ require_extension('F');
 require_fp;
 bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
             (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
   WRITE_FRD(f32(defaultNaNF32UI));
+else
+  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;
-- 
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