Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2011-02-15 | [xcc,opcodes,pk,sim] krste's re-renaming spree | Andrew Waterman | 40 | -93/+93 | |
2011-02-15 | [xcc,sim,opcodes] removed mtflh/mffl/mffh | Andrew Waterman | 4 | -24/+0 | |
in rv32 these will be replaced with loads and stores. | |||||
2011-02-04 | [sim,pk] added interrupt-pending field to cause reg | Andrew Waterman | 5 | -13/+13 | |
2011-02-02 | [sim,xcc,opcodes] added back mtflh.d | Andrew Waterman | 3 | -5/+11 | |
2011-02-02 | [opcodes,pk,sim,xcc] synci now bombs whole icache | Andrew Waterman | 1 | -9/+9 | |
2011-02-01 | [xcc,opcodes,pk,sim] cleanup to FP ISA | Andrew Waterman | 10 | -137/+114 | |
- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64 | |||||
2011-02-01 | [sim] added nearest/ties to max magnitude rounding mode | Andrew Waterman | 1 | -3/+7 | |
2011-01-26 | [sim] changed divide-by-0 semantics | Andrew Waterman | 2 | -9/+8 | |
now it always gives -1, no matter the signedness. | |||||
2011-01-25 | [sim,opcodes] add mulhsu instruction | Andrew Waterman | 2 | -1/+14 | |
2011-01-25 | [opcodes,pk,sim,xcc] great renumbering of 2011, part deux | Andrew Waterman | 4 | -536/+529 | |
2011-01-20 | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | Andrew Waterman | 84 | -151/+186 | |
2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 59 | -137/+155 | |
now generic variants behave differently in RV32 and RV64. | |||||
2011-01-17 | [opcodes, pk, sim, xcc] removed nor, normalized macros to addi | Andrew Waterman | 2 | -6/+0 | |
2011-01-11 | [sim] fix jalr bug | Andrew Waterman | 1 | -1/+1 | |
2011-01-03 | [opcodes,pk,sim,xcc] flip fields to favor little endian | Yunsup Lee | 2 | -162/+166 | |
2010-12-27 | [sim] fixed some compiler warnings | Andrew Waterman | 5 | -4/+5 | |
2010-12-27 | [sim] cleaned up handling of link register | Andrew Waterman | 2 | -1/+2 | |
2010-11-21 | [sim] handle integer division overflow | Andrew Waterman | 8 | -12/+32 | |
Behavior is now same as GCC's optimizer. Previously, we just crashed :) | |||||
2010-11-21 | [opcodes, pk, sim, xcc] Tweaked FP encoding | Andrew Waterman | 67 | -347/+94 | |
2010-11-21 | [opcodes] generate latex and verilog correctly | Andrew Waterman | 1 | -67/+67 | |
2010-11-21 | [pk] various PK cleanups/speedups | Andrew Waterman | 2 | -0/+2 | |
2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 167 | -513/+517 | |
2010-11-21 | [xcc, sim, pk] link register is now x1 | Andrew Waterman | 2 | -1/+6 | |
2010-11-21 | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | Andrew Waterman | 2 | -35/+4 | |
2010-10-26 | [sim] removed unnecessary trap in mfcr instruction | Andrew Waterman | 1 | -3/+0 | |
2010-10-26 | [sim,xcc] fixed minor bugs related to tp/cr29 | Andrew Waterman | 1 | -3/+0 | |
2010-10-26 | [pk,sim,xcc] get rid of at register, introduce tp register | Yunsup Lee | 4 | -6/+2 | |
2010-10-25 | [sim,xcc,pk,opcodes] static rounding modes for FP insns | Andrew Waterman | 38 | -46/+353 | |
Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.) | |||||
2010-10-15 | [pk, sim] added FPU emulation support to proxy kernel | Andrew Waterman | 4 | -2/+29 | |
2010-10-11 | [sim] added writeback tracing | Andrew Waterman | 1 | -2/+26 | |
2010-10-07 | [xcc] modified opcodes for better FP decode mapping | Andrew Waterman | 1 | -27/+19 | |
2010-10-05 | [opcodes] added code field back to syscall/break | Andrew Waterman | 1 | -2/+2 | |
2010-10-05 | [xcc] removed CEXC field from FSR | Andrew Waterman | 1 | -15/+5 | |
2010-10-05 | [xcc,sim] eliminated vectored traps | Andrew Waterman | 5 | -7/+13 | |
now, the evec register holds the address that all traps vector to, and the cause register is set with the trap number. | |||||
2010-10-02 | [sim, xcc] changed cvt/trunc to use GPRs for int args | Andrew Waterman | 16 | -16/+24 | |
this way, we don't have to futz with storing integers in recoded floating-point registers. too bad we lose some decoupling. | |||||
2010-10-02 | [xcc, sim] mff now uses rs2 for data | Andrew Waterman | 5 | -49/+49 | |
this is symmetric with fp stores, so we only need one decoding pipe | |||||
2010-09-28 | [opcodes, sim, xcc] added mffl.d instruction | Andrew Waterman | 2 | -108/+115 | |
...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu | |||||
2010-09-23 | [xcc, sim] eliminated zero-extended immediates | Andrew Waterman | 4 | -6/+5 | |
This is a big commit because it involved rewriting gcc's algorithm for generating constants. | |||||
2010-09-22 | [sim] fixed bug in which shift operands were reversed | Andrew Waterman | 6 | -6/+6 | |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 145 | -243/+245 | |
2010-09-13 | [xcc, sim] replaced ble/bleu with bge/bgeu | Andrew Waterman | 5 | -11/+11 | |
This will simplify control logic (since every branch has a logical inverse) | |||||
2010-09-12 | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 7 | -29/+29 | |
2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 14 | -87/+72 | |
2010-09-12 | [xcc, sim] branches now are next-PC-based, not PC-based | Andrew Waterman | 3 | -8/+8 | |
2010-09-11 | [xcc] fixed broken 32-bit FP ABI | Andrew Waterman | 1 | -0/+0 | |
2010-09-10 | [sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit | Andrew Waterman | 4 | -5/+9 | |
2010-09-10 | [sim, pk] cleaned up exception vectors and FP exc flags | Andrew Waterman | 3 | -15/+24 | |
2010-09-10 | [opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit) | Yunsup Lee | 3 | -147/+148 | |
2010-09-09 | [opcodes,sim,xcc] move opcodes for 3 source instructions | Yunsup Lee | 1 | -56/+67 | |
2010-09-09 | Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu" | Andrew Waterman | 5 | -4/+4 | |
This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison. |