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2023-06-17Add test that ensures opcodes don't overlap unless explicitly specifiedAndrew Waterman2-1/+59
2023-06-17Add C.EBREAK, C.JALR, and C.JR to overlap listAndrew Waterman1-0/+3
This isn't a functional change; we just failed to notate that C.EBREAK and C.JALR overlap C.ADD, and C.JR overlaps C.MV.
2023-06-12Merge pull request #1376 from YenHaoChen/pr-cbo-regionAndrew Waterman1-1/+1
Fix: PMP checking region on CBO instructions
2023-06-12Fix PMP checking region of cache-block management instructionsYenHaoChen1-1/+1
The spec says "The PMP access control bits shall be the same for all physical addresses in the cache block [... else] the behavior of a CBO instruction is UNSPECIFIED." Thus, we only need to check the byte rs1 points to (instead of the entire cache block).
2023-06-08Replace ternary operator with std:mindemin.han1-2/+2
2023-06-06Merge pull request #1321 from plctlab/plct-bf16-devAndrew Waterman16-7/+176
Add support for BF16 extensions
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome4-12/+20
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-29Add flh/fsh/fmv_h_x/fmv_x_h instructions to Zvfbfmin/Zvfbfwma extensionsWeiwei Li6-4/+9
2023-05-29Add support for new instructions of Zvfbfwma extensionWeiwei Li4-0/+69
2023-05-29Add support for new instructions of Zvfbfmin extensionWeiwei Li4-0/+37
2023-05-29Add support for new instructions of Zfbfmin extensionWeiwei Li4-2/+22
2023-05-29Update encoding.h to add instructions for BF16 extensionsWeiwei Li1-1/+22
2023-05-29Add isa string support for Zfbfmin/Zvfbfmin/ZvfbfwmaWeiwei Li2-0/+17
2023-05-27Merge pull request #1368 from glg-rv/have_int128/0/topicJerry Zhao3-7/+7
Minor fixes (mostly related to __int128 support)
2023-05-26Fix check for extensionGianluca Guida1-1/+1
Calling 'extension_enabled' this early during the constructor of 'processor_t' causes SIGSEGV.
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida3-6/+6
Make sure that the configure decision on 128-bit is consistent during compilation. Also move uint128_t definition.
2023-05-26decode_macros: move 'is_aligned' from 'v_ext_macros.h'Gianluca Guida2-5/+4
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman6-38/+12
This cleans up the code and avoids bugs like #1365.
2023-05-25Move setting of V=0 for M-mode trapScott Johnson1-1/+1
So it's right next to set_privilege() which it will be combined with next.
2023-05-25Move setting of V=0 for HS-mode trapScott Johnson1-1/+1
So it's right next to set_privilege() which it will be combined with next.
2023-05-25Explicitly use the nonvirtual S-mode CSRs when going to HS-modeScott Johnson2-12/+19
Since we're going to move the change to state->v next.
2023-05-25Force V=1 when going to VS-mode trap handlerScott Johnson1-0/+1
Should already be 1.
2023-05-25Redo sret to put set_virt/set_privilege togetherScott Johnson1-3/+4
2023-05-25Prevent possibility of V=1 and PRV=M when entering debug modeAndrew Waterman1-0/+1
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman4-3/+11
Resolves #1365
2023-05-25Use more descriptive variable name in dcsr_csr_t::read; make it reg_tAndrew Waterman1-12/+12
2023-05-24triggers: Fix etrigger match on exceptionsAtul Khare2-4/+7
The etrigger match on exceptions doesn't work properly in cases like the following: 1) M-mode delegates ECALLs to S-mode 2) A CPU hardware point mechanism is used to place a breakpoint on the Umode instruction that executes the ECALL from Umode to Smode. In effect, this creates a breakpoint etrigger based on Umode. In the above, the expectation is that #2 will first cause an exit to the Smode handler (stvec), and the hardware breakpoint exception will be triggered following an entry into the handler. However, since etrigger currently checks the current privilege mode, we will never get a match on conditions like #2. The patch attempts to address the issue by using the stashed version of the previous privilege mode for the etrigger match. cc: YenHaoChen <howard25336284@gmail.com> Signed-off-by: Atul Khare <atulkhare@rivosinc.com>
2023-05-24Enhance mode_match() functionalityAtul Khare2-6/+7
The current version of mode_match() is based on the current privilege level. This adds an explicit privilege and virtual mode parameters in anticipation of an upcoming patch for matching trap triggers.
2023-05-24Add prev_prv to processor stateAtul Khare2-1/+3
This adds the prev_prv field to track the previous privilege. It will be used in a forthcoming patch for trigger matching.
2023-05-24Add pre_v to processor stateAtul Khare2-12/+12
This adds the prev_v field to track the previous virtual mode state. We also assign it unconditionally to handle cases for trigger matching like the following (pointed out by Scott Johnson): 1) SRET from HS to VU: prev_v is set to 0 2) Trap from VU to VS: state.v/prev_v won't be assigned because of unchanged v, and remain 0. 3) An etrigger that's set to break on a VU-mode trap won't match properly because prev_v is incorrect This be used in a forthcoming patch for trigger matching.
2023-05-23Let mstatus.MPP initially be M-mode if unsupporting U-modeYenHaoChen1-0/+1
This commit lets the mstatus.MPP be a valid value if unsupporting U-mode. Without this commit, the mret may result in a corrupted state without properly setting the MPP to M-mode (if unsupporting U-mode).
2023-05-19Add Spike's meta files for pkg-configWojciech Bartczak1-0/+2
This commit adds the *.pc files for Spike's simulation library, enabling dynamic and static linking without the need to directly reference Spike sources. Using Spike as a stand-alone library provides an interesting option for developing tools and applications based on Spike.
2023-05-11Use passed in virtual bit for creating traps in take_trigger_action() rahter ↵rbuchner1-1/+1
than state.v Fixes case 1 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner6-16/+17
2023-05-11Add split_misaligned_access() to mem_access_info_trbuchner2-2/+6
2023-05-11Pass mem_access_info_t into walk()rbuchner2-4/+8
2023-05-11Use access_info within store_slow_path rather than xlate_flagsRyan Buchner1-1/+1
2023-05-11Use access_info.effective_virt when failed mmio_store (i.e. device detects ↵rbuchner1-1/+1
access fault) Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Adjust store_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner2-8/+10
2023-05-11Use access_info within load_slow_path rather than xlate_flagsRyan Buchner1-2/+2
Fixes case 2 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Use access_info.effective_virt when failed mmio_load (i.e. device detects ↵rbuchner1-1/+1
access fault) Fixes case 3 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Use access_info.effective_virt when access_fault due to non-reservable lrrbuchner1-1/+1
Fixes case 4 from https://github.com/riscv-software-src/riscv-isa-sim/issues/872
2023-05-11Adjust load_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner2-10/+12
2023-05-11Add structure (mem_access_info_t) for holding memory access informationRyan Buchner2-21/+41
Add complementary function for generating access information. Update mmu_t::translate() to accept a mem_access_info_t.
2023-05-11Add is_special_access() to xlate_flags_trbuchner2-6/+10
2023-05-11Add xlate_flags_t structrbuchner2-38/+52
Use xlate_flags_t rather than XLATE_FLAGS preprocessing directives
2023-05-11Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRTRyan Buchner2-7/+7
More readable/understandable.
2023-05-09Merge pull request #1357 from ptomsich/ptomsich/1312-fix-fcvtmod_w_d-exceptionsAndrew Waterman1-1/+3
Zfa: fix exception behaviour for fcvtmod.w.d
2023-05-09Merge pull request #1356 from ptomsich/ptomsich/1355-fix-fleq-fltq-exceptionsAndrew Waterman8-0/+8
Zfa: fix missing set_fp_exceptions for fleq/fltq
2023-05-09Zfa: fix missing set_fp_exceptions for fleq/fltqPhilipp Tomsich8-0/+8
generated by cgit v1.1 at 2024-10-19 09:29:04 +0000